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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.
Design and development of low noise microwave PCM-FM breadboard telemetry transmitters and receivers
Staying up to date with the latest CAD tools both from a cost and time perspective is difficult. Within a given organization there may be experts in Printed Circuit Board Design tools and experts in FPGA/VHDL tools. Wouldn't it be great to have someone familiar with HDL Designer be able to design PCBs without having to learn another tool? This paper describes a limited experiment to do this.
The overall objective of the program is to provide the engineering tools to reduce the analysis, design, and development effort, and thus the cost, in achieving the required performances for switching regulators and dc-dc converter systems. The program was both tutorial and application oriented. Various analytical methods were described in detail and supplemented with examples, and those with standardization appeals were reduced into computer-based subprograms. Major program efforts included those concerning small and large signal control-dependent performance analysis and simulation, control circuit design, power circuit design and optimization, system configuration study, and system performance simulation. Techniques including discrete time domain, conventional frequency domain, Lagrange multiplier, nonlinear programming, and control design synthesis were employed in these efforts. To enhance interactive conversation between the modeling and analysis subprograms and the user, a working prototype of the Data Management Program was also developed to facilitate expansion as future subprogram capabilities increase.
Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.
Achieving brain-like efficiency in computing requires a co-design between the development of neural algorithms, brain-inspired circuit design, and careful consideration of how to use emerging devices. The recognition that leveraging device-level noise as a source of controlled stochasticity represents an exciting prospect of achieving brain-like capabilities in probabilistic neural algorithms, but the reality of integrating stochastic devices with deterministic devices in an already-challenging neuromorphic circuit design process is formidable. Here, we explore how the brain combines different signaling modalities into its neural circuits as well as consider the implications of more tightly integrated stochastic, analog, and digital circuits. Further, by acknowledging that a fully CMOS implementation is the appropriate baseline, we conclude that if mixing modalities is going to be successful for neuromorphic computing, it will be critical that device choices consider strengths and limitations at the overall circuit level.
Design equations for hysteresis circuit are based on the following assumptions: amplifier input impedance is larger than source impedance; amplifier output impedance is less than load impedance; and amplifier switches state when differential input voltage is approximately zero. Circuits are designed to any given specifications.
Precisely arranged sets of dye molecules can utilized as elementary quantum computing elements. Here, we consider two different strategies for designing these excitonic circuits for a 2-qubit multi-step quantum algorithm.
This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.
Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.
Correlations and measures of entanglement in ground-state wave functions of relativistic quantum field theories are spatially localized over length scales set by the mass of the field. We utilize this localization to design digital quantum circuits for preparing the ground states of lattice scalar quantum field theories. Controlled rotations that are exponentially localized in their position-space extent are found to provide exponentially convergent wave function fidelity. These angles scale with the correlation between sites and the classical two-point correlation function, as opposed to the more localized mutual information or the hyperlocalized (1×1)-site negativity. We anticipate that further investigations will uncover quantum circuit designs with controlled rotations dictated by the measures of entanglement. This work is expected to impact quantum simulations of systems of importance to nuclear physics, high-energy physics, and basic energy sciences research.
Monitoring circuit design for sampling circuit control and reduction of time-bandwidth in video communication systems
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.
Design options for utility-interactive photovoltaic power conditioning technology for unit ratings from 2kW to 5 MW are compared. Line- and self-commutated inverter designs for both single and three-phase applications are described. Efficiency, weight, and cost projections are provided for comparing the design options. New circuit designs that take advantage of advances in power semiconductor devices are found to be the most promising. Hardware efficiencies from 95 percent for single phase to 98 percent for three-phase applications are found.
This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.
We present experimental results and a validated numerical model of a dual-circuit phase-change thermal energy storage module for air conditioners. The module incorporates a phase-change material encapsulated in compressed expanded natural graphite foam. We used n-tetradecane as the PCM with a transition temperature (~4.5 °C) suitable for air-conditioning applications. Heat exchange to and from the module is accomplished through two fluid loops operating as a heat source and sink embedded inside multiple slabs of the composite material. This dual-circuit design enables easier integration with air-conditioning equipment and provides enhanced flexibility in system operation as compared to the state-of-the-art thermal storage systems. When integrated with an air-conditioner, this design will enable peak-load shaving and enhances operational efficiency. The thermal storage device was designed for a nominal storage capacity of ~ 3.5 kWh. We evaluated the heat transfer and energy storage performance of this device using standalone heat transfer experiments to estimate key thermal resistances and identify design improvements before integration with an air conditioner. The numerical model of the heat exchanger uses a combination of discretized and lumped parameter approaches to maintain a balance between accuracy and computational expense. Our analyses show that the geometric features and integration of fluid tubes are key contributors to the thermal contact resistance between the fluid and the thermal storage material, and consequently, to the overall performance of the thermal storage module. Our standalone experiments also identified important operating scenarios in which this thermal storage module can be used for air-conditioning in buildings.
The concept of designing for reliability will be introduced along with a brief overview of reliability, redundancy and traditional methods of fault tolerance is presented, as applied to current logic devices. The fundamentals of advanced circuit design and analysis techniques will be the primary focus. The introduction will cover the definitions of key device parameters and how analysis is used to prove circuit correctness. Basic design techniques such as synchronous vs asynchronous design, metastable state resolution time/arbiter design, and finite state machine structure/implementation will be reviewed. Advanced topics will be explored such as skew-tolerant circuit design, the use of triple-modular redundancy and circuit hazards, device transients and preventative circuit design, lock-up states in finite state machines generated by logic synthesizers, device transient characteristics, radiation mitigation techniques. worst-case analysis, the use of timing analyzer and simulators, and others. Case studies and lessons learned from spaceflight designs will be given as examples
This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.