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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Fault-tolerant computer architecture based on INMOS transputer processor

Redundant processing was used for several years in mission flight systems. In these systems, more than one processor performs the same task at the same time but only one processor is actually in real use. A fault-tolerance computer architecture based on the features provided by INMOS Transputers is presented. The Transputer architecture provides several communication links that allow data and command communication with other Transputers without the use of a bus. Additionally the Transputer allows the use of parallel processing to increase the system speed considerably. The processor architecture consists of three processors working in parallel keeping all the processors at the same operational level but only one processor is in real control of the process. The design allows each Transputer to perform a test to the other two Transputers and report the operating condition of the neighboring processors. A graphic display was developed to facilitate the identification of any problem by the user.

Ortiz, Jorge L.↗
NASA NTRS1976

The unified data system - A distributed processing network for control and data handling on a spacecraft

This paper presents the results obtained in a continuing investigation of real-time distributed processing systems which is being conducted at the Jet Propulsion Laboratory. A distributed processor architecture has been developed for control and data handling on a planetary spacecraft. This system, designated the Unified Data System, has been implemented in a feasibility breadboard. The following aspects of the Unified Data System are described: (1) standardized building block elements and their configuration into microprocessor modules, (2) a highly redundant bus structure which connects the various modules and facilitates intercommunications with minimal software support, (3) the structure of software within the individual modules and its coordination between modules, and (4) the mechanisms by which fault-tolerance can be implemented within the network. Through the attributes of multilevel standardization, simplicity, and flexibility, this system is expected to result in significant cost savings to future spacecraft missions.

Rennels, D. A.↗
NASA NTRS1988

Reliability Model Generator for fault-tolerant systems

This paper discusses an analysis tool, the Reliability Model Generator, that reasons from structural and functional system design specifications to generate a reliability model for the system under investigation. The resultant model defines a system state space sufficient to characterize the effects of single and multiple component failures. This model may then be examined by the analyst or used as input to an existing reliability evaluation tool, the Semi-Markov Unreliability Range Evaluator (SURE), to compute numeric bounds for system reliability (i.e., safety, mission success, availability, etc.). In defining the input to the Reliability Model Generator, a separation of the component function from structural specification is proposed to allow easy modification for analysis of alternative architectures. A hierarchical system description paradigm promotes multiple abstractions, thereby enabling analysis at all phases of the design process. The work described in this paper has been supported under NASA contract NAS1-10899, Integrated Airframe/Propulsion Control System Architecture (IAPSA II). IAPSA II promotes a system engineering methodology and supporting analytical tools to evaluate flight control architecture configuration alternatives during early phases of the design cycle when the cost and schedule impact of design revisions is minimal. Emphasis is placed on traceability to ensure that the requirements drive the resulting design.

Catherine M McCann↗
NASA NTRS1971

Logic design for dynamic and interactive recovery.

Recovery in a fault-tolerant computer means the continuation of system operation with data integrity after an error occurs. This paper delineates two parallel concepts embodied in the hardware and software functions required for recovery; detection, diagnosis, and reconfiguration for hardware, data integrity, checkpointing, and restart for the software. The hardware relies on the recovery variable set, checking circuits, and diagnostics, and the software relies on the recovery information set, audit, and reconstruct routines, to characterize the system state and assist in recovery when required. Of particular utility is a handware unit, the recovery control unit, which serves as an interface between error detection and software recovery programs in the supervisor and provides dynamic interactive recovery.

Carter, W. C.↗
NASA NTRS1973

Highly reliable processor system for space application.

Description of a redundant processor organization which can be implemented with off-the-shelf processors for fault-tolerant operation. Reconfiguration can be performed automatically in a transientless manner. To support this system configuration and redundancy management concept, an operating system referred to as a synchronous executive has been designed. This system is directed at real-time closed-loop space applications where minimum response time, no degradation of software solution, and system simplicity are of importance. The system is based on a multicomputer organization with each machine solving the same problem based on a common set of inputs. Processor status is fed to a higher-level device which selects a controlling processor for controlling outputs and monitoring computers for fault detection.

Tsou, H. S. E.↗
NASA NTRS1978

Critical fault patterns determination in fault-tolerant computer systems

The method proposed tries to enumerate all the critical fault-patterns (successive occurrences of failures) without analyzing every single possible fault. The conditions for the system to be operating in a given mode can be expressed in terms of the static states. Thus, one can find all the system states that correspond to a given critical mode of operation. The next step consists in analyzing the fault-detection mechanisms, the diagnosis algorithm and the process of switch control. From them, one can find all the possible system configurations that can result from a failure occurrence. Thus, one can list all the characteristics, with respect to detection, diagnosis, and switch control, that failures must have to constitute critical fault-patterns. Such an enumeration of the critical fault-patterns can be directly used to evaluate the overall system tolerance to failures. Present research is focused on how to efficiently make use of these system-level characteristics to enumerate all the failures that verify these characteristics.

Mccluskey, E. J.↗
NASA NTRS1981

A tutorial on the CARE III approach to reliability modeling

The CARE 3 reliability model for aircraft avionics and control systems is described by utilizing a number of examples which frequently use state-of-the-art mathematical modeling techniques as a basis for their exposition. Behavioral decomposition followed by aggregration were used in an attempt to deal with reliability models with a large number of states. A comprehensive set of models of the fault-handling processes in a typical fault-tolerant system was used. These models were semi-Markov in nature, thus removing the usual restrictions of exponential holding times within the coverage model. The aggregate model is a non-homogeneous Markov chain, thus allowing the times to failure to posses Weibull-like distributions. Because of the departures from traditional models, the solution method employed is that of Kolmogorov integral equations, which are evaluated numerically.

Trivedi, K. S.↗
NASA NTRS1983

Specifying and Verifying Ultra-reliability and Fault-tolerance Properties

A methodology to rigorously verify ultrareliability and fault tolerance system properties is described. The methodology utilizes a hierarchy of formal mathematical specifications of system design and incremental design proof to prove the system has the desired properties. A small example of the approach is given, and the application of the methodology to the large scale proof of SIFT, a fault tolerant flight control operating system, is discussed.

Schwartz, R. L.↗
NASA NTRS1984

Software Implemented Fault-Tolerant (SIFT) user's guide

Program development for a Software Implemented Fault Tolerant (SIFT) computer system is accomplished in the NASA LaRC AIRLAB facility using a DEC VAX-11 to interface with eight Bendix BDX 930 flight control processors. The interface software which provides this SIFT program development capability was developed by AIRLAB personnel. This technical memorandum describes the application and design of this software in detail, and is intended to assist both the user in performance of SIFT research and the systems programmer responsible for maintaining and/or upgrading the SIFT programming environment.

Green, D. F., Jr.↗
NASA NTRS1985

Redundant Asynchronous Microprocessor System

Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.

Meyer, G.↗
NASA NTRS1987

Characterization of fault recovery through fault injection on FTMP

The development of fault-injection procedures and statistical analysis techniques to characterize the fault recovery of fault-tolerant systems is described. Pin-level fault-injection was conducted on a fault-tolerant microprocessor computer in order to generate data to assess the utility of current fault-injection sampling methods. The validity of common reliability-modeling assumptions concerning the statistical distribution of recovery times is investigated. A multiple comparison analysis for detecting behavior variations, and a distribution fitting for determining the best fit for the data were conducted. It is observed that the detection behavior is not homogeneous across all data sets, and that none of the factors under experimental control can account for the observed groupings of behavior. It is determined that no single distribution fits all the data sets, and that stratified random sampling and statistically robust parameter-estimation techniques are required to characterize fault detection time.

Finelli, George B.↗
NASA NTRS1981

Digital avionics design and reliability analyzer

The description and specifications for a digital avionics design and reliability analyzer are given. Its basic function is to provide for the simulation and emulation of the various fault-tolerant digital avionic computer designs that are developed. It has been established that hardware emulation at the gate-level will be utilized. The primary benefit of emulation to reliability analysis is the fact that it provides the capability to model a system at a very detailed level. Emulation allows the direct insertion of faults into the system, rather than waiting for actual hardware failures to occur. This allows for controlled and accelerated testing of system reaction to hardware failures. There is a trade study which leads to the decision to specify a two-machine system, including an emulation computer connected to a general-purpose computer. There is also an evaluation of potential computers to serve as the emulation computer.

Source record↗
NASA NTRS1987

Fault-tolerant clock synchronization validation methodology

A validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight-crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating the clock synchronization system of the Software Implemented Fault Tolerance computer. The design proof of the algorithm includes a theorem that defines the maximum skew between any two nonfaulty clocks in the system in terms of specific system parameters. Most of these parameters are deterministic. One crucial parameter is the upper bound on the clock read error, which is stochastic. The probability that this upper bound is exceeded is calculated from data obtained by the measurement of system parameters. This probability is then included in a detailed reliability analysis of the system.

Computer systems↗
NASA NTRS1989

Study of a unified hardware and software fault-tolerant architecture

A unified architectural concept, called the Fault Tolerant Processor Attached Processor (FTP-AP), that can tolerate hardware as well as software faults is proposed for applications requiring ultrareliable computation capability. An emulation of the FTP-AP architecture, consisting of a breadboard Motorola 68010-based quadruply redundant Fault Tolerant Processor, four VAX 750s as attached processors, and four versions of a transport aircraft yaw damper control law, is used as a testbed in the AIRLAB to examine a number of critical issues. Solutions of several basic problems associated with N-Version software are proposed and implemented on the testbed. This includes a confidence voter to resolve coincident errors in N-Version software. A reliability model of N-Version software that is based upon the recent understanding of software failure mechanisms is also developed. The basic FTP-AP architectural concept appears suitable for hosting N-Version application software while at the same time tolerating hardware failures. Architectural enhancements for greater efficiency, software reliability modeling, and N-Version issues that merit further research are identified.

Lala, Jaynarayan↗
NASA NTRS1986

An Ada implementation for fault detection, isolation and reconfiguration using a fault-tolerant processor

The design and implementation, in Ada, of the Fault Detection, Isolation, and Reconfiguration (FDIR) Manager for the triply redundant, tightly synchronized, Fault Tolerant Processor (FTP) are covered. It also examines the suitability of Ada, in the context of the FTP, for real time control tasks. The operational concepts behind the FTP are explained, and the structure of the resultant Ada code is discussed.

Greeley, Gregory L.↗
NASA NTRS1989

Implementing fault-tolerant sensors

One aspect of fault tolerance in process control programs is the ability to tolerate sensor failure. A methodology is presented for transforming a process control program that cannot tolerate sensor failures to one that can. Additionally, a hierarchy of failure models is identified.

Marzullo, Keith↗
NASA NTRS1990

Measurement and analysis of workload effects on fault latency in real-time systems

The authors demonstrate the need to address fault latency in highly reliable real-time control computer systems. It is noted that the effectiveness of all known recovery mechanisms is greatly reduced in the presence of multiple latent faults. The presence of multiple latent faults increases the possibility of multiple errors, which could result in coverage failure. The authors present experimental evidence indicating that the duration of fault latency is dependent on workload. A synthetic workload generator is used to vary the workload, and a hardware fault injector is applied to inject transient faults of varying durations. This method makes it possible to derive the distribution of fault latency duration. Experimental results obtained from the fault-tolerant multiprocessor at the NASA Airlab are presented and discussed.

Woodbury, Michael H.↗