Results for “hardware” — Page 6

NASA NTRS2024

Exploration Extravehicular Mobility Unit (xEMU) Chamber B Thermal Vacuum “Suit 2” Pressure Garment System Hardware and Test Design

NASA’s Exploration Extravehicular Mobility Unit (xEMU) is the government reference next-generation space suit design and is engineered to protect astronauts from extreme lunar environmental temperatures. To evaluate the xEMU hardware thermal requirements, the xEMU Testing Team invented, designed, and executed a dual-suit, uncrewed thermal vacuum (TVAC) test at Johnson Space Center’s (JSC) Chamber B. This paper details the test hardware design and test methodology for the “Suit 2” Pressure Garment System (PGS) test article. The uncrewed “Suit 2” PGS test article consisted of a full PGS assembly with simulated Portable Life Support System (PLSS) functionality provided by test equipment, including a ventilation loop and two distinct thermal control loops. This paper will discuss in depth the test hardware design, including internal suit thermal boundary simulation, sensor quantity and placement, test support equipment rigs for gas flow, water flow, and power. Custom hardware designed to add additional penetrations to the suit or provide additional interfaces for sensors will also be discussed. This paper will also address the assembly and integration sequence for the test article. In addition to test hardware design, this paper will provide insights into the test methodology for this test article, including a discussion of thermal steady-state testing, simultaneous dual suit thermal vacuum testing, and hazard mitigation and controls.

xEMU↗

NASA NTRS2024

Interoperability Review of Wireless Hardware in Emergency Air-To-Ground Mesh Networks

The air-to-ground network has the goal of advancing the capabilities and versatility of communications in wildfire and emergency scenarios. To ensure compatibility and keep costs low for emergency services interoperability between hardware is an important step in development of the mesh network. For the purposes of this evaluation interoperability of hardware is described as the ability for hardware from different vendors to be interchangeable within the network with minimal initial setup and no functional change from an operator’s viewpoint. This report will also focus on the features and limitations in addition to the interoperability of the major wireless hardware systems core to the function of the proposed air-to-ground mesh network. The hardware systems involved are ADS-B receivers, 3GPP Sidelink devices, mesh radios, and commercial ISM band radios. For early testing the mesh radios will be in the 900 MHz frequency range using the DoodleLabs RM-1700-22W Mesh Rider Radio as the lab reference. This report will consider and categorize desirability of features, the amount of setup required before deployment, the effect on performance characteristics from nominal and maximum load, and the ability to interface with other vender devices.

Mesh Radio↗

DOE OSTI2025

Uncontrolled Learning: Codesign of Neuromorphic Hardware Topology for Neuromorphic Algorithms

Neuromorphic computing has the potential to revolutionize future technologies and our understanding of intelligence, yet it remains challenging to realize in practice. The learning-from-mistakes algorithm, inspired by the brain's simple learning rules of inhibition and pruning, is one of the few brain-like training methods. This algorithm is implemented in neuromorphic memristive hardware through a codesign process that evaluates essential hardware trade-offs. While the algorithm effectively trains small networks as binary classifiers and perceptrons, performance declines significantly with increasing network size unless the hardware is tailored to the algorithm. This work investigates the trade-offs between depth, controllability, and capacity—the number of learnable patterns—in neuromorphic hardware. This highlights the importance of topology and governing equations, providing theoretical tools to evaluate a device's computational capacity based on its measurements and circuit structure. The findings show that breaking neural network symmetry enhances both controllability and capacity. Additionally, by pruning the circuit, neuromorphic algorithms in all-memristive circuits can utilize stochastic resources to create local contrasts in network weights. Through combined experimental and simulation efforts, the parameters are identified that enable networks to exhibit emergent intelligence from simple rules, advancing the potential of neuromorphic computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2026

Evaluation of Hardware and Software Bill of Materials (HBOMs/SBOMs) Extraction Methods

Hardware and software bills of materials (HBOMs and SBOMs) provide important visibility into the components, dependencies, and supply chain relationships within programmable digital devices. This visibility is critical for advanced nuclear reactor applications, where use of common or shared hardware components, software libraries, suppliers, or manufacturing processes may create common cause failure (CCF) vulnerabilities despite apparent diversity. This paper evaluates current approaches for obtaining and analyzing HBOMs and SBOMs in support of CCF, diversity and defense-in-depth (D3) assessments, and begins to explore potential methods for artificial intelligence/machine learning-based analysis. The availability of BOM information from advanced reactor manufacturers and vendors, representative hardware and software categories found in advanced reactor systems continues to limit research [13]. This paper compares commonly used BOM formats, including CycloneDX, SPDX, and SWID. It also surveys publicly available tools for generating BOMs from source code, compiled binaries, and hardware-related information, noting limitations in language coverage, system age, and format interoperability. Finally, this paper evaluates methods for correlating BOM data with vulnerability and exploitability information, including VEX, CVE, and CWE resources. The findings indicate that publicly available nuclear-vendor BOMs are limited, making third-party extraction and research into novel analysis techniques necessary.

Cybersecurity↗

DOE OSTI2025

Nuclear Thermal Rocket Emulator for a Hardware-in-the-Loop Test Bed

To support NASA’s mission to use nuclear thermal rockets for future Mars missions, an instrumentation and control test bed has been built at Oak Ridge National Laboratory. The system is designed as a hardware-in-the-loop test bed for testing control elements and autonomous control algorithms for nuclear thermal propulsion rockets. The mock reactor system consists of a modular and scalable framework, using inexpensive components and open-source software. The hardware system consists of a two-phase flow loop and a mock reactor with six control drums. A single-board computer (NVIDIA Jetson) handles reactor core emulation and hosts a message queuing telemetry transport broker that allows user-deployed control algorithms to interact with the system hardware. The reactor emulator receives sensor data from the hardware and provides the simulated performance of the reactor under steady-state, transient, and fault conditions. The emulator uses a reactivity lookup table and the point kinetics equations to solve for the reactor dynamics in real time. Emulated reactor dynamics and sensor input inform the autonomous control algorithm’s decision-making in a closed-loop manner. The current system is capable of operating at 10 Hz, but faster cycle rates are an area of ongoing research. This test bed will enable NASA and other space vendors to rigorously test their autonomous control systems for NTP rockets under transient (reactor startup and shutdown), steady-state, and fault conditions to reduce development time and risk for autonomous control systems in future missions.

autonomous control↗

NASA NTRS2000

Speed challenge: a case for hardware implementation in soft-computing

For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

neural networks fuzzy logic evolvable hardware sof↗

NASA NTRS2002

Evolvable, reconfigurable hardware for future space systems

This paper overviews Evolvable Hardware (EHW) technology, examining its potential for enhancing survivability and flexibility of future space systems. EHW refers to selfconfiguration of electronic hardware by evolutionary/genetic search mechanisms. Evolvable Hardware can maintain existing functionality in the presence of faults and degradations due to aging, temperature and radiation. It can also configure itself for new functionality when required for mission changes or encountered opportunities. The paper illustrates hardware evolution in silicon using a JPL-designed programmable device reconfigurable at transistor level as the platform and a genetic algorithm running on a DSP as the reconfiguration mechanism. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The experiments demonstrate functional recovery from faults as well as from degradation at extreme temperatures indicating the possibility of expanding the operational range of extreme electronics through evolved circuit solutions.

Evolvable Hardware EHW↗

NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗

NASA NTRSDate not supplied

Development, Build and Certification of the Alternate Fecal Canister (AFC) Hardware for the NASA Exploration Toilet

On longer range exploration missions, the mass and volume of critical hardware and consumables that will be needed to support crew will pose a big stowage challenge. This includes the hardware needed for the collection and storage of human metabolic waste. The amount of stowage needed for this hardware both before (empty) and after (full) use will be a significant burden on the overall spacecraft habitable volume, layout, and design. To help with this challenge, the National Aeronautics and Space Administration (NASA) has developed a collapsible canister for the collection and containment of fecal deposits. The Alternate Fecal Canister (AFC) is an alternative to the exploration toilet hard-sided fecal canister. The AFC is collapsible in its empty state which is a volume benefit to smaller vehicles on longer missions. In addition, the use of lighter-weight materials provides a reduction in mass of the overall container. This paper will provide a summary of the AFC design including final flight design and build, acceptance and qualification testing completed, final certification and delivery and forward plans for a technology demonstration with the exploration toilet on the International Space Station (ISS). In addition, a summary of issues and final resolution encountered during flight build and testing will also be provided. As part of the acceptance and certification process for AFC, the hardware was also put into several rounds of odor testing with the support of the White Sands Test Facility (WSTF). The details, planning and anomalies identified during odor testing will also be summarized in this paper. Finally, a brief overview of potential future design upgrades including changes to address any crew feedback from the ISS demonstration will be discussed.

Fecal Canister↗

NASA NTRSDate not supplied

Development, Build and Certification of the Alternate Fecal Canister (AFC) Hardware for the NASA Exploration Toilet

On longer range exploration missions, the mass and volume of critical hardware and consumables that will be needed to support crew will pose a big stowage challenge. This includes the hardware needed for the collection and storage of human metabolic waste. The amount of stowage needed for this hardware both before (empty) and after (full) use will be a significant burden on the overall spacecraft habitable volume, layout, and design. To help with this challenge, the National Aeronautics and Space Administration (NASA) has developed a collapsible canister for the collection and containment of fecal deposits. The Alternate Fecal Canister (AFC) is an alternative to the exploration toilet hard-sided fecal canister. The AFC is collapsible in its empty state which is a volume benefit to smaller vehicles on longer missions. In addition, the use of lighter-weight materials provides a reduction in mass of the overall container. This paper will provide a summary of the AFC design including final flight design and build, acceptance and qualification testing completed, final certification and delivery and forward plans for a technology demonstration with the exploration toilet on the International Space Station (ISS). In addition, a summary of issues and final resolution encountered during flight build and testing will also be provided. As part of the acceptance and certification process for AFC, the hardware was also put into several rounds of odor testing with the support of the White Sands Test Facility (WSTF). The details, planning and anomalies identified during odor testing will also be summarized in this paper. Finally, a brief overview of potential future design upgrades including changes to address any crew feedback from the ISS demonstration will be discussed.

Fecal Canister↗

NASA NTRSDate not supplied

Development, Build and Certification of the Alternate Fecal Canister (AFC) Hardware for the NASA Exploration Toilet

On longer range exploration missions, the mass and volume of critical hardware and consumables that will be needed to support crew will pose a big stowage challenge. This includes the hardware needed for the collection and storage of human metabolic waste. The amount of stowage needed for this hardware both before (empty) and after (full) use will be a significant burden on the overall spacecraft habitable volume, layout, and design. To help with this challenge, the National Aeronautics and Space Administration (NASA) has developed a collapsible canister for the collection and containment of fecal deposits. The Alternate Fecal Canister (AFC) is an alternative to the exploration toilet hard-sided fecal canister. The AFC is collapsible in its empty state which is a volume benefit to smaller vehicles on longer missions. In addition, the use of lighter-weight materials provides a reduction in mass of the overall container. This paper will provide a summary of the AFC design including final flight design and build, acceptance and qualification testing completed, final certification and delivery and forward plans for a technology demonstration with the exploration toilet on the International Space Station (ISS). In addition, a summary of issues and final resolution encountered during flight build and testing will also be provided. As part of the acceptance and certification process for AFC, the hardware was also put into several rounds of odor testing with the support of the White Sands Test Facility (WSTF). The details, planning and anomalies identified during odor testing will also be summarized in this paper. Finally, a brief overview of potential future design upgrades including changes to address any crew feedback from the ISS demonstration will be discussed.

Fecal Canister↗

DOE OSTI2025

A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans

The complexity of the semiconductor design lifecycle and globalized manufacturing process creates concern over the threat of deliberate malicious alterations, or hardware Trojans, being inserted into microelectronic designs. This has resulted in a significant corpus of hardware Trojan research including Trojan design and benchmarking efforts and development of corresponding metrics and detection and prevention techniques, over the last two decades. In this survey, we first highlight efforts in Trojan design and benchmarking, followed by a cataloging of seminal and recent works in Trojan detection and prevention and their accompanied metrics. Given the volume of literature in this field, this survey considers only pre-silicon techniques. We make this distinction between pre- and post-silicon to properly scope and provide appropriate context into the capabilities of existing hardware Trojan literature. Each major section (design, prevention, and detection) is accompanied by insights, and common pitfalls, which we highlight can be addressed by future research.

42 ENGINEERING↗

DOE OSTI2025

Efficient Simulation of Open Quantum Systems on NISQ Trapped‐Ion Hardware

Abstract Simulating open quantum systems, which interact with external environments, presents significant challenges on noisy intermediate‐scale quantum (NISQ) devices due to limited qubit resources and noise. In this study, an efficient framework is proposed for simulating open quantum systems on NISQ hardware by leveraging a time‐perturbative Kraus operator representation of the system's dynamics. This approach avoids the computationally expensive Trotterization method and exploits the Lindblad master equation to represent time evolution in a compact form, particularly for systems satisfying specific commutation relations. The efficiency of this method is demonstrated by simulating quantum channels, such as the continuous‐time Pauli channel and damped harmonic oscillators, on NISQ trapped‐ion hardware, including IonQ Harmony and Quantinuum H1‐1. Additionally, hardware‐agnostic error mitigation techniques are introduced, including Pauli channel fitting and quantum depolarizing channel inversion, to enhance the fidelity of quantum simulations. These results show strong agreement between the simulations on real quantum hardware and exact solutions, highlighting the potential of Kraus‐based methods for scalable and accurate simulation of open quantum systems on NISQ devices. This framework opens pathways for simulating more complex systems under realistic conditions in the near term.

Burdine, Colin [Department of Electrical and Compu↗

DOE OSTI2024

On the emerging potential of quantum annealing hardware for combinatorial optimization

Abstract Over the past decade, the usefulness of quantum annealing hardware for combinatorial optimization has been the subject of much debate. Thus far, experimental benchmarking studies have indicated that quantum annealing hardware does not provide an irrefutable performance gain over state-of-the-art optimization methods. However, as this hardware continues to evolve, each new iteration brings improved performance and warrants further benchmarking. To that end, this work conducts an optimization performance assessment of D-Wave Systems’ Advantage Performance Update computer, which can natively solve sparse unconstrained quadratic optimization problems with over 5,000 binary decision variables and 40,000 quadratic terms. We demonstrate that classes of contrived problems exist where this quantum annealer can provide run time benefits over a collection of established classical solution methods that represent the current state-of-the-art for benchmarking quantum annealing hardware. Although this work does not present strong evidence of an irrefutable performance benefit for this emerging optimization technology, it does exhibit encouraging progress, signaling the potential impacts on practical optimization tasks in the future.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

DOE OSTI2026

Balance of Plant Modeling and Real-Time Hardware-in-the-Loop Integration with the Microreactor Automated Control System

The advent of novel microreactor technology has driven a focused effort to explore safety and efficiency improvements that can be achieved through the use of automated system control. Development of control strategies, especially for initial demonstration, requires an adequate surrogate environment to safely research failure modes and control integration with realistic hardware delay. However, efficiency gains from control strategies are improved when the scope of controller action is expanded to include system-level dynamics such as downstream heat extraction and mass flow. For this reason, a balance-of-plant (BOP) model of a representative microreactor system has been developed using the TRANsient Simulation Framework of Reconfigurable Models library in Modelica. This model captures a reactor and primary NaK coolant loop that represent corresponding system components of the Microreactor Applications Research Validation and EvaLuation (MARVEL) design as well as a secondary coolant loop and heat extraction representative of the Microreactor Agile Non-Nuclear Experimental Test Bed (MAGNET). This model configuration allows for hardware-in-the-loop (HIL) integration with microreactor automated control system (MACS) hardware in real time through a Python-based gRPC client. Real-time simulation of model performance with emulated hardware and communication delay suggests that under independent proportional-integral-derivative control of BOP model drum dynamics and downstream heat extraction, stable power load following is achievable. A slight delay in load following, filtering of high-frequency dynamics, and localized temperature fluctation suggest room for improvement through the development of higher-level control strategies. The simulated coupling of the MAGNET facility lays the groundwork for future digital twin analysis with a coupled MACS-MAGNET HIL demonstration.

McConnell, Jono [ORNL] (ORCID:0000000238984741)↗

DOE OSTI2024

HPC Network Simulation Tuning via Automatic Extraction of Hardware Parameters

Popular HPC network interconnection simulators such as SST/macro provide a variety of configurable parameters to explore the design space of hardware components such as network interface cards (NIC), switches, and links among them. While such knobs provide flexibility to explore design trade-offs for novel hardware, manually configuring simulations for matching configurations of the existing hardware to focus on topology exploration can be cumbersome and error-prone, leading to widely inaccurate simulations. This challenge is compounded when specifications of various (proprietary) technologies are not readily available or intentionally omitted. In this work, we propose a framework to autotune the multiple network models’ simulation configurations within SST/macro using Tree-structured Parzen Estimator-based Bayesian optimization to observe the effect on simulation accuracy across different message regimes. These regimes consist of small to large message sizes and latency to bandwidth-bound messages. We provide a detailed analysis of the simulation error for four representative HPC systems. Our Bayesian optimization based autotuning framework for network models achieves a maximum of 5x improvement in accuracy over best-effort manual configurations based on available hardware specifications.

Simulation, autotuning↗

DOE OSTI2026

Data-driven analysis to understand GPU hardware resource usage of optimizations

With heterogeneous systems, the number of GPUs per chip increases to provide computational capabilities for solving science at a nanoscopic scale. However, low utilization for single GPUs defies the need to invest more money in expensive accelerators. Although related work develops optimizations to improve application performance, none studies how these optimizations impact hardware resource usage or average GPU utilization. Here, this paper takes a data-driven analysis approach in addressing this gap by (1) characterizing how hardware resource usage affects device utilization, execution time, or both, (2) presenting a multiobjective metric to identify important application-device interactions that can be optimized to improve device utilization and application performance jointly, (3) studying hardware resource usage behaviors of several optimizations for a benchmark application, and finally (4) identifying optimization opportunities for several scientific proxy applications based on their hardware resource usage behaviors. Furthermore, we demonstrate the applicability of our methodology by applying the identified optimizations to a proxy application, which improves the execution time, device utilization, and power consumption by up to 29.6%, 5.3% and 26.5% respectively.

Computer science↗

DOE OSTI2026

Lifetime extension of legacy CEBAF LLRF hardware

A significant portion of the Low-Level Radio Frequency (LLRF) hardware in Jefferson Lab’s CEBAF is from the original construction of the facility using 1980’s CAMAC technology. Of the fifty-three zones in CEBAF, thirty-six of them are legacy hardware. The age of the legacy system has led to difficulties in maintaining the hardware due to parts going obsolete without suitable drop in replacements. Continued operation of the legacy system is required as the installation of LLRF 3.0 systems is costly and cannot be completed in a short period of time with the available resources. The most pressing failure in the legacy system was a failing buffer card, which is responsible for communication between the EPICs network and individual RF control modules. A new buffer card was designed as a transparent, drop in, replacement so that upgrades are simply a matter of swapping the existing legacy hardware. This buffer card upgrades a single point failure component and promises to extend the operable lifetime of CEBAF’s legacy systems.

Accelerator Physics↗