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Papers are presented dealing with the design of reliable, low cost, advanced avionics systems applicable to general aviation in the 1980's and beyond. Sensors, displays, integrated circuits, microprocessors, and minicomputers are among the topics discussed.
Electro-optic, polymer-based integrated optic devices for high-speed communication and computing applications offer potentially significant advantages over conventional inorganic electro-optic crystals. One key area of integrated optical technology--primary processing and fabrication--may particularly benefit from the use of polymer materials. However, as efforts concentrate on the miniaturization of electro-integrated circuit pattern geometries, the ability to etch fine features and smoothly sloped sidewalls is essential to make polymers useful for electro-integrated circuit applications. There are many existing processes available to etch polymer materials, but they all yield nearly vertical sidewalls. Vertical sidewalls are too difficult to reliably cover with a metal layer, and incomplete metalization degrades microwave performance, particularly at high frequency. However, obtaining a very sloped sidewall greatly improves the deposition of metal on the sidewall, leading to low-loss characteristics, which are essential to integrating these devices in highspeed electro-optic modulators. The NASA Lewis Research Center has developed in-house an inexpensive etching technique that uses a photolithography method followed by a simple, wet chemical etching process to etch through polymer layers. In addition to being simpler and inexpensive, this process can be used to fabricate smoothly sloped sidewalls by using a commercial none rodible mask: Spin-On-Glass. A commercial transparent material, Spin-On-Glass, uses processes and equipment similar to that for photoresist techniques.
This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.
The engineering development of a solid-state transmitter amplifier operating in the 20-GHz frequency range is described. This effort involved a multitude of disciplines including IMPATT device development, circulator design, multiple-diode circuit design, and amplifier integration and test. The objective was to develop a transmitter amplifier demonstrating the feasibility of providing an efficient, reliable, lightweight solid-state transmitter to be flown on a 30 to 20 GHz communication demonstration satellite. The work was done under contract from NASA/Lewis Research Center for a period of three years. The result was the development of a GaAs IMPACT diode amplifier capable of an 11-W CW output power and a 2-dB bandwidth of 300 MHz. GaAs IMPATT diodes incorporating diamond heatsink and double-Read doping profile capable of 5.3-W CW oscillator output power and 15.5% efficiency were developed. Up to 19% efficiency was also observed for an output power level of 4.4 W. High performance circulators with a 0.2 dB inserting loss and bandwidth of 5 GHz have also been developed. These represent a significant advance in both device and power combiner circuit technologies in K-band frequencies.
The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.
Compact device uses transformerless capacitor/diode voltage multiplier. Advantages include efficiency at high power levels, increased reliability due to elimination of magnetics and associated electrical transients, no magnetic shielding requirement, and adaptability to modular or integrated circuit systems.
Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.
Scanning phased-array antennas represent a highly desirable solution for futuristic near-Earth and deep space communication scenarios requiring vibration-free, rapid beam steering and enhanced reliability. The current state-of-practice in scanning phased arrays is represented by gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC) technology or ferrite phase shifters. Cost and weight are significant impediments to space applications. Moreover, conventional manifold-fed arrays suffer from beam-forming loss that places considerable burden on MMIC amplifiers. The inefficiency can result in severe thermal management problems.
The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.
Two reliable fault-tolerant coding schemes have been proposed for state machines that are used in field-programmable gate arrays and application-specific integrated circuits to implement sequential logic functions. The schemes apply to strings of bits in state registers, which are typically implemented in practice as assemblies of flip-flop circuits. If a single-event upset (SEU, a radiation-induced change in the bit in one flip-flop) occurs in a state register, the state machine that contains the register could go into an erroneous state or could hang, by which is meant that the machine could remain in undefined states indefinitely. The proposed fault-tolerant coding schemes are intended to prevent the state machine from going into an erroneous or hang state when an SEU occurs. To ensure reliability of the state machine, the coding scheme for bits in the state register must satisfy the following criteria: 1. All possible states are defined. 2. An SEU brings the state machine to a known state. 3. There is no possibility of a hang state. 4. No false state is entered. 5. An SEU exerts no effect on the state machine. Fault-tolerant coding schemes that have been commonly used include binary encoding and "one-hot" encoding. Binary encoding is the simplest state machine encoding and satisfies criteria 1 through 3 if all possible states are defined. Binary encoding is a binary count of the state machine number in sequence; the table represents an eight-state example. In one-hot encoding, N bits are used to represent N states: All except one of the bits in a string are 0, and the position of the 1 in the string represents the state. With proper circuit design, one-hot encoding can satisfy criteria 1 through 4. Unfortunately, the requirement to use N bits to represent N states makes one-hot coding inefficient.
Planetary exploration missions and deep space probes require electrical power management and control systems that are capable of efficient and reliable operation in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures will not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures; thereby reducing system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior and tolerance in the electrical and thermal properties of semiconductor and dielectric materials at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial-off-the-shelf as well as developed components that are being characterized include switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being investigated for potential use in low temperature applications. An overview of the NASA Glenn Research Center Low Temperature Electronic Program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained through in-house component and circuit testing will also be discussed. Ongoing research activities that are being performed in collaboration with various organizations will also be presented.
The Si-gate CMOS/SOS process used to manufacture integrated circuits is examined. A process analysis test structure is developed to determine the defect mechanisms most detrimental to yield, control, and reliability.
Dual-function integrated circuits use one shift register array instead of two to feed video data to seven tape channels thereby making system more reliable and less expensive than predecessor. Basic principle of reformatter is also applicable to multiplexing and frequency conversion circuits.
Radar electronics developed for past JPL space missions historically had been custom designed and as such, given budgetary, time, and risk constraints, had not been optimized for maximum flexibility or miniaturization. To help reduce cost and risk of future radar missions, a generic radar module was conceived. The module includes a 1.25-GHz (L-band) transceiver and incorporates miniature high-density packaging of integrated circuits in die/chip form. The technology challenges include overcoming the effect of miniaturization and high packaging density to achieve the performance, reliability, and environmental ruggedness required for space missions. The module was chosen to have representative (generic) functionality most likely required from an L-band radar. For very large aperture phased-array spaceborne radar missions, the large dimensions of the array suggest the benefit of distributing the radar electronics into the antenna array. For such applications, this technology is essential in order to bring down the cost, mass, and power of the radar electronics module replicated in each panel of the array. For smaller sized arrays, a single module can be combined with the central radar controller and still provide the bene.ts of configuration .exibility, low power, and low mass. We present the design approach for the radar electronics module and the test results for its radio frequency (RF) portion: a miniature, low-power, radiation-hard L-band transceiver.
The objective of this study is to develop a new methodology for estimating the reliability of engineering systems that encompass multiple disciplines. The methodology is formulated in the context of the NESSUS probabilistic structural analysis code developed under the leadership of NASA Lewis Research Center. The NESSUS code has been successfully applied to the reliability estimation of a variety of structural engineering systems. This study examines whether the features of NESSUS could be used to investigate the reliability of systems in other disciplines such as heat transfer, fluid mechanics, electrical circuits etc., without considerable programming effort specific to each discipline. In this study, the mechanical equivalence between system behavior models in different disciplines are investigated to achieve this objective. A new methodology is presented for the analysis of heat transfer, fluid flow, and electrical circuit problems using the structural analysis routines within NESSUS, by utilizing the equivalence between the computational quantities in different disciplines. This technique is integrated with the fast probability integration and system reliability techniques within the NESSUS code, to successfully compute the system reliability of multi-disciplinary systems. Traditional as well as progressive failure analysis methods for system reliability estimation are demonstrated, through a numerical example of a heat exchanger system involving failure modes in structural, heat transfer and fluid flow disciplines.
The objective of this study is to develop a new methodology for estimating the reliability of engineering systems that encompass multiple disciplines. The methodology is formulated in the context of the NESSUS probabilistic structural analysis code, developed under the leadership of NASA Glenn Research Center. The NESSUS code has been successfully applied to the reliability estimation of a variety of structural engineering systems. This study examines whether the features of NESSUS could be used to investigate the reliability of systems in other disciplines such as heat transfer, fluid mechanics, electrical circuits etc., without considerable programming effort specific to each discipline. In this study, the mechanical equivalence between system behavior models in different disciplines are investigated to achieve this objective. A new methodology is presented for the analysis of heat transfer, fluid flow, and electrical circuit problems using the structural analysis routines within NESSUS, by utilizing the equivalence between the computational quantities in different disciplines. This technique is integrated with the fast probability integration and system reliability techniques within the NESSUS code, to successfully compute the system reliability of multidisciplinary systems. Traditional as well as progressive failure analysis methods for system reliability estimation are demonstrated, through a numerical example of a heat exchanger system involving failure modes in structural, heat transfer and fluid flow disciplines.
Many bipolar integrated circuits are much more susceptible to ionizing radiation at low dose rates than they are at high dose rates typically used for radiation parts testing. Since the low dose rate is equivalent to that seen in space, the standard lab test no longer can be considered conservative and has caused the Air Force to issue an alert. Although a reliable radiation hardness assurance test has not yet been designed, possible mechanisms for low dose rate enhancement and hardness assurance tests are discussed.
Planetary exploration missions and deep space probes require electrical power management and control systems that can operate efficiently and reliably in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units to maintain the surrounding temperature of the onboard electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures would not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures. Thereby, such electronics would reduce system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results because semiconductor and dielectric materials have better behavior and tolerance in their electrical and thermal properties at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center is focusing on the research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and in deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial off-the-shelf as well as developed components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, dc-dc converters, operational amplifiers, and oscillators are also being investigated for potential use in low-temperature applications. For example, the output response of an advanced oscillator at room temperature and at -190 C is shown. Most oscillators can operate at temperatures down to only -55 C. It can be seen that, for this oscillator, the low temperature of -196 C changed the leading and trailing edges of the oscillator pulses by producing overshoot. The research and development efforts performed under the Low Temperature Electronics Program at Glenn are being carried out through collaboration with other Government agencies, industrial and aerospace companies, and academia. The program supports missions as well as technology development efforts at NASA's Goddard Space Flight Center and Langley Research Center, and the Jet Propulsion Laboratory.