Search NASA⌕ Search

SEARCH · Search NASA

Results for “integrated circuit testing”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 109 records · Page 6

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗

Comparison of Hafnium Dioxide and Zirconium Dioxide Grown by Plasma-Enhanced Atomic Layer Deposition for the Application of Electronic Materials

We report the growth of nanoscale hafnium dioxide (HfO 2 ) and zirconium dioxide (ZrO 2 ) thin films using remote plasma-enhanced atomic layer deposition (PE-ALD), and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using the HfO 2 and ZrO 2 thin films as the gate oxide. Tetrakis (dimethylamino) hafnium (Hf[N(CH 3 ) 2 ] 4 ) and tetrakis (dimethylamino) zirconium (IV) (Zr[N(CH 3 ) 2 ] 4 ) were used as the precursors, while O 2 gas was used as the reactive gas. The PE-ALD-grown HfO 2 and ZrO 2 thin films were analyzed using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). The XPS measurements show that the ZrO 2 film has the atomic concentrations of 34% Zr, 2% C, and 64% O while the HfO 2 film has the atomic concentrations of 29% Hf, 11% C, and 60% O. The HRTEM and XRD measurements show both HfO 2 and ZrO 2 films have polycrystalline structures. n-channel and p-channel metal-oxide semiconductor field-effect transistors (nFETs and pFETs), CMOS inverters, and CMOS ring oscillators were fabricated to test the quality of the HfO 2 and ZrO 2 thin films as the gate oxide. Current-voltage (IV) curves, transfer characteristics, and oscillation waveforms were measured from the fabricated transistors, inverters, and oscillators, respectively. The experimental results measured from the HfO 2 and ZrO 2 thin films were compared.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Comparative Analysis of Heat Exchangers for High Temperature High Pressure Helium Component Testing

Helium gas loops have been designed and built to gain a better understanding of the gas thermohydraulic phenomena that take place in a helium system. Some of these loops are used for validation and testing of components for high temperature gas-cooled reactors (HTGRs). However, most of them operate at lower pressure and temperature than an HTGR. While these loops can provide valuable information about gas-cooled reactor components, the operating envelope of the experiment is constrained by the maximum operating conditions of the helium loop. In response to the lack of an experimental facility that can provide the infrastructure needed to validate and test components at nominal pressures and temperatures of HTGRS, the HElium Component Testing Out-of-pile Research (HECTOR) facility was designed at Idaho National Laboratory with the assistance of University of Idaho and Walsh Engineering. With the capability to test at temperatures up to 800°C and pressures of 8MPa, HECTOR serves as a critical tool for the advancement of HTGR technology. The facility's primary role is to provide a controlled, high-fidelity environment for the assessment of component resilience and efficiency under nominal HTGR conditions. In the quest to enhance the efficiency and performance of HECTOR, a comparative analysis of three distinct types of heat exchangers—shell and tube, offset strip fin, and printed-circuit—was conducted, focusing primarily on two critical metrics: the required surface area and pressure drop characteristics. The shell and tube heat exchanger, renowned for its robust design and widespread industrial application, was evaluated against the offset strip fin and the cuttingedge printed-circuit heat exchangers, both of which are lauded for their compactness and thermal effectiveness. This comparative study aims to provide detailed insights into the thermal management capabilities of each heat exchanger type under the conditions inherent to HECTOR, thereby facilitating an informed selection for systems demanding high operational integrity and efficiency.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

High-Density, Actively Multiplexed µECoG Array on Reinforced Silicone Substrate

Simultaneous interrogation of electrical signals from wide areas of the brain is vital for neuroscience research and can aid in understanding the mechanisms of brain function and treatments for neurological disorders. There emerges a demand for development of devices with highly conformal interfaces that can span large cortical regions, have sufficient spatial resolution, and chronic recording capability while keeping a small implantation footprint. In this work, we have designed 61 channel and 48 channel high-density, cortical, micro-electrocorticographic electrode arrays with 400 µm pitch on an ultra-soft but durable substrate. We have also developed a custom multiplexing integrated circuit (IC), methods for packaging the IC in a water-tight liquid crystal polymer casing, and a micro-bonding method for attaching the electronics package to the electrode array. With the integrated multiplexer, the number of external wire connections can be reduced to 16 wires, thereby diminishing the invasive footprint of the device. Both the electrode array and IC were tested in vivo in a rat model to demonstrate the ability to sense finely-localized electrophysiological signals.

Rachinskiy, Iakov↗

Combined Environments: Driving multiple loads on Z

Pulsed power drivers such as the Z generator of Sandia National Laboratories typically deliver high current (>20MA) to single experiments. This project is intended to develop and assess ways to simultaneously drive multiple targets on a single pulsed power driver (specifically a neutron and an x-ray producing target driven in a single experiment). The combined x-ray/neutron environment produced will then be used to investigate potential synergistic effects in integrated circuits. A pre-requisite for being able to design and study multiple targets on Z is first adapting simulation tools to be able to model them effectively. This will enable us to assess the tradeoffs between the different ways multiple targets can be combined, and to better understand how existing and future pulsed power machines can be used to generate combined testing environments. This report is limited to documenting the initial development of a parallel load modeling capability that is presently being applied to design experiments to produce combined neutron/x-ray environments on Z.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Advanced CMOS Reliability Update: Sub 20nm FinFET Assessment

Advances in FinFET design and fabrication enable manufacturing of denser, more compact integrated circuits (ICs) with substantially reduced leakage while shortening the channel-lengths. The same stress-induced leakage and breakdown degradation mechanisms that affect planar transistors also impact FinFET devices. Reliability concerns such as Bias Temperature Instability (BTI), Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Injection (HCI) become very important with changes to transistor geometry and fin sidewall crystal orientation. Recent testing has shown that FinFETs respond differently to radiation (radiation effects such as total ionizing dose) when compared to planar transistors. These reliability and radiation effects issues become very important when changing transistor geometry and scaling FinFETs towards smaller feature sizes (22-nm, 16-nm, 14- nm, 10-nm, and smaller critical dimensions). The comparable 2019 state of the art transistor densities in current high-volume manufacturing silicon-based foundries is 7-nm (ISMC, Samsung) and 10-nm (Intel) [www.anandtech.com,fuse.wikichip.org]. Released products include supporting components for the cellphone and commercial microprocessor markets respectively. Extensive development in the foundry industry is driving to a 5-nm technology node in late 2020.

47 OTHER INSTRUMENTATION↗

On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application

To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.

Wongk, Nicole↗

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Finally, further development of the eFPGA technology and its application to collider detector readout is discussed.

47 OTHER INSTRUMENTATION↗

Functional and Evolutionary Integration of a Fungal Gene With a Bacterial Operon

Abstract Siderophores are crucial for iron-scavenging in microorganisms. While many yeasts can uptake siderophores produced by other organisms, they are typically unable to synthesize siderophores themselves. In contrast, Wickerhamiella/Starmerella (W/S) clade yeasts gained the capacity to make the siderophore enterobactin following the remarkable horizontal acquisition of a bacterial operon enabling enterobactin synthesis. Yet, how these yeasts absorb the iron bound by enterobactin remains unresolved. Here, we demonstrate that Enb1 is the key enterobactin importer in the W/S-clade species Starmerella bombicola. Through phylogenomic analyses, we show that ENB1 is present in all W/S clade yeast species that retained the enterobactin biosynthetic genes. Conversely, it is absent in species that lost the ent genes, except for Starmerella stellata, making this species the only cheater in the W/S clade that can utilize enterobactin without producing it. Through phylogenetic analyses, we infer that ENB1 is a fungal gene that likely existed in the W/S clade prior to the acquisition of the ent genes and subsequently experienced multiple gene losses and duplications. Through phylogenetic topology tests, we show that ENB1 likely underwent horizontal gene transfer from an ancient W/S clade yeast to the order Saccharomycetales, which includes the model yeast Saccharomyces cerevisiae, followed by extensive secondary losses. Taken together, these results suggest that the fungal ENB1 and bacterial ent genes were cooperatively integrated into a functional unit within the W/S clade that enabled adaptation to iron-limited environments. This integrated fungal-bacterial circuit and its dynamic evolution determine the extant distribution of yeast enterobactin producers and cheaters.

59 BASIC BIOLOGICAL SCIENCES↗

Development of a dynamical model and energy analysis for wheel loader

The objective of this paper is to develop a fully integrated model for the wheel loader, including the subsystem dynamics of the engine, drivetrain, working circuit, steering circuit, and vehicle. It leads to a high-order strongly nonlinear system, and all state variables are coupled together to form a Multi-Input and Multi-Output (MIMO) system. A control architecture is proposed to decouple the MIMO system into several Single-Input and Single-Output (SISO) systems. Here, a tracking problem has been formulated to validate this fully integrated model with the field test data. The accuracy of the model is verified by the 2.3% difference between the measured and simulated fuel consumption. Meanwhile, an energy distribution analysis is conducted to reveal the energy consumption and energy loss of each portion of the wheel loader. Such a model can be used to plan the working pattern, guide the driving habits of human operators, or refine the underlying architecture, leading to the ultimate goal of reducing total fuel consumption and improving productivity.

42 ENGINEERING↗

Introducing the 9500 Node Distribution Test System to Support Advanced Power Applications: An Operations-Focused Approach

The 9500 Node Test System is a representative section of distribution power system model developed as a part of the GridAPPS-D™ project, an effort funded by DOE as a part of the Grid Modernization Lab Consortium (GMLC) program. The test system was developed to fulfill a growing need to represent the rapidly evolving state of electric distribution systems by combining elements of legacy infrastructure systems, modern feeder topologies, and an anticipated future with smart grid technologies. It also provides a network model capable of supporting the simulation of operational scenarios such as the ones in a utility distribution control center. This test system allows the evaluation of the performance of advanced power applications in real-time, such as one that simulates the operations of an Advanced Distribution Management Systems (ADMS), Distributed Energy Resource Management Systems (DERMS), etc. in a Distribution control center. This model is an extension of the widely used IEEE 8500 Node Test Feeder and is currently being validated to become an IEEE test case to help increase adoption and widespread usage among both academia and industry. It is a full-size model representative of a section of a utility’s distribution system with multiple feeders fed from different substations. The model includes multiple distribution circuits, a sub-transmission system, multiple substations, behind the meter customer rooftop photovoltaics (PV), and multiple utility-scale distributed energy resources. To enable accurate simulations of operational scenarios, the 9500 Node Test System is designed to support procedure-based operations, with the ability to realistically demonstrate switching operations, feeder reconfiguration, adjustment of volt-var control equipment, dispatch of distributed generation, and response to planned and unplanned outages. The 9500 Node Test System includes three radial distribution feeders with 12.3 MVA of average load, consisting of both medium voltage and low voltage equipment each supplied by a different distribution substation. The three distribution feeders are connected to each other through Normally-Open switches which can be closed when needed to simulate restoration scenarios due to a fault. One feeder represents today’s grid with low penetration of customer-side renewables. The second represents a potential future grid with microgrids and 100% renewable penetration. The third has no customer generation resources, a district steam plant, and a utility-scale solar farm. The three diverse circuits were created to allow the simulation of both today’s situation as well as potential future scenarios. All three feeders have customers connected by low-voltage secondary triplex lines. This test system meets all requirements outlined in the report for creating a simulation environment that would enable discussion between key technical stakeholders as well as having the potential to accelerate operational application development and their subsequent testing and integration. The new model is a possible representation of what we believe the distribution grid may look like in the future: a high penetration of renewables, reconfigurable radial and mesh topology, numerous DERs, islanded microgrids, and significantly increased data and measurement density. The system supports both the solution of existing and newer algorithms but also enables the evaluation of applications in a realistic operational environment defined by task oriented procedural steps that represent the interaction between the control center operator and field personnel.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Cold Trap Replacement Project Report

This report documents the replacement of the Mechanisms Engineering Test Loop (METL) cold trap. The work involved preparation of the facility to replace the cold trap, removal of the existing welded cold trap from the sodium purification circuit, installation of a new replacement cold trap, completion of associated welds and examinations, restoration of instrumentation and heaters, and controlled return of the cold trap circuit to service. The replacement represented a significant maintenance evolution because the cold trap is an integral welded component of the sodium system. As a result, the work required coordinated control of sodium chemistry, deliberate formation of freeze plugs, inert gas management, precision cutting and welding, and a staged reheating and refill sequence. The activity was executed using procedural controls intended to protect personnel, preserve system cleanliness, and maintain the integrity of the sodium boundary throughout the work. This report provides a narrative summary of the milestone, including the purpose of the work, the pre-job system condition, the major field activities performed, observations made during execution, and the resulting post-work condition of the METL cold trap circuit.

42 ENGINEERING↗

3x3 array module of 8×8×32 mm 3 position-sensitive virtual frisch-grid CdZnTe detectors for imaging and spectroscopy of cosmic gamma-rays

Here, we evaluated the performance of the 3x3 array of 32-mm long position-sensitive virtual Frisch-grid (VFG) CdZnTe (CZT) detectors read out by the IDEAS GDS-100 data acquisition system. The array is a mechanically solid module designed for integration into a large effective area gamma-ray telescope proposed for imaging and spectroscopy of cosmic gamma-rays. The array employs the bar-shaped 8x8x32 mm 3 CZT crystals which recently became available from Redlen Technologies, Inc. and Kromek-eV Group PLC at affordable costs. The waveform sampling IDE3421 application-specific integrated circuit (ASIC), developed by the University of Michigan and IDEAS for CZT pixel detectors, was adapted to capture the signals from the array's VFG detectors. We showed good spectral performance of the Redlen detectors with an energy resolution of <1% FWHM at 662 keV and slightly poorer performance of the Kromek-eV detectors with a resolution of <2% measured at a reduced temperature of 13 °C. By testing the same detectors as single devices using hybrid charge-sensitive preamplifiers, we demonstrated improved energy resolutions at a normal temperature of ~25°C: <1% and 1.3-1.7%, respectively. However, the Kromek-eV detectors did not perform as well as the Redlen ones. We explained this by the space charge formation (polarization) decreasing the electric field and the electron drift times. The polarization was likely caused by the high injections of holes from the anode contacts. The absence of polarization in Redlen detectors suggested that the quality of the contacts might have played a role in this case.

47 OTHER INSTRUMENTATION↗

Energy efficient photonic memory based on electrically programmable embedded III-V/Si memristors: switches and filters

Abstract Over the past few years, extensive work on optical neural networks has been investigated in hopes of achieving orders of magnitude improvement in energy efficiency and compute density via all-optical matrix-vector multiplication. However, these solutions are limited by a lack of high-speed power power-efficient phase tuners, on-chip non-volatile memory, and a proper material platform that can heterogeneously integrate all the necessary components needed onto a single chip. We address these issues by demonstrating embedded multi-layer HfO 2 /Al 2 O 3 memristors with III-V/Si photonics which facilitate non-volatile optical functionality for a variety of devices such as Mach-Zehnder Interferometers, and (de-)interleaver filters. The Mach-Zehnder optical memristor exhibits non-volatile optical phase shifts > π with ~33 dB signal extinction while consuming 0 electrical power consumption. We demonstrate 6 non-volatile states each capable of 4 Gbps modulation. (De-) interleaver filters were demonstrated to exhibit memristive non-volatile passband transformation with full set/reset states. Time duration tests were performed on all devices and indicated non-volatility up to 24 hours and beyond. We demonstrate non-volatile III-V/Si optical memristors with large electric-field driven phase shifts and reconfigurable filters with true 0 static power consumption. As a result, co-integrated photonic memristors offer a pathway for in-memory optical computing and large-scale non-volatile photonic circuits.

Cheung, Stanley (ORCID:0000000248860013)↗

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 x16 pixel matrix.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Sensors with Intelligent Measurement Platform for Monitoring and Control in Distribution Circuits

This paper presents a medium-voltage intelligent measurement platform that provides post-processing of raw measurements received from commercially-available voltage/current sensors to enhance accuracy and bandwidth of the monitoring system. Furthermore, this platform integrates into a Data Distribution Service (DDS) messaging bus for distributed control and interoperability. The authors present the design, specifications, and major components included in the platform, and argue for applications and use cases that most benefit from this new approach. A laboratory testbed has been created to demonstrate the functionality, for which test results are presented for selected test cases.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Error mitigation, optimization, and extrapolation on a trapped-ion testbed

Current noisy intermediate-scale quantum (NISQ) trapped-ion devices are subject to errors which can significantly impact the accuracy of calculations if left unchecked. A form of error mitigation called zero noise extrapolation (ZNE) can decrease an algorithm’s sensitivity to these errors without increasing the number of required qubits. Here we explore different methods for integrating this error mitigation technique into the Variational Quantum Eigensolver (VQE) algorithm for calculating the ground state of the HeH + molecule at 0.8 Å in the presence of experimental noise. Using the Quantum Scientific Computing Open User Testbed (QSCOUT) trapped-ion device, we test three methods of scaling noise for extrapolation: time stretching the two-qubit gates, scaling the sideband detuning parameter, and inserting two-qubit gate identity operations into the ansatz circuit. We find that time stretching and sideband detuning scaling fail to scale the noise on our particular hardware in a way that can be extrapolated to zero noise. Scaling our noise with global gate identity insertions and extrapolating after variational optimization, we achieve error suppression of 96.8%, resulting in an energy estimate within –0.004 ± 0.04 hartree of the ground state energy. This is an improvement, but still outside the chemical accuracy threshold of 0.0016 hartree. Furthermore, our results show that the efficacy of this error mitigation technique depends on choosing the correct implementation for a given device architecture.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Wide-field microwave magnetic field imaging with nitrogen-vacancy centers in diamond

Non-invasive imaging of microwave (MW) magnetic fields with microscale lateral resolution is pivotal for various applications, such as MW technologies and integrated circuit failure analysis. Diamond nitrogen-vacancy (NV) center magnetometry has emerged as an ideal tool, offering micrometer-scale resolution, millimeter-scale field of view, high sensitivity, and non-invasive imaging compatible with diverse samples. However, up until now, it has been predominantly used for imaging of static or low-frequency magnetic fields or, concerning MW field imaging, to directly characterize the same microwave device used to drive the NV spin transitions. In this work, we leverage an NV center ensemble in diamond for wide-field imaging of MW magnetic fields generated by a test device employing a differential measurement protocol. The microscope is equipped with a MW loop to induce Rabi oscillations between NV spin states, and the MW field from the device-under-test is measured through local deviations in the Rabi frequency. This differential protocol yields magnetic field maps of a 2.57 GHz MW field with a sensitivity of ∼9 μT Hz −1/2 for a total measurement duration of T=357 s, covering a 340 × 340 μm 2 field of view with a micrometer-scale spatial resolution and a device-under-test input power dynamic range of 30 dB. This work demonstrates a novel NV magnetometry protocol, based on differential Rabi frequency measurement, that extends NV wide-field imaging capabilities to imaging of weak MW magnetic fields that would be difficult to measure directly through standard NV Rabi magnetometry.

crystallographic defects↗