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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Environmental Testing of Flight Hardware in the 25 ft. Space Simulator at JPL in a Manual Mode

After receiving global admiration for the Mars Science Laboratory (MSL) Curiosity rover, the Jet Propulsion Laboratory (JPL) is planning to embark upon another mobile mission to the red planet in the year 2020. Currently, the working name given to this sophisticated next-generation rover is Mars 2020. Mars 2020 will boast a multitude of newly developed instruments to aid in the scientific study of Mars. This paper will describe the process of testing one of the Mars 2020 instruments in the 25 ft. Space Simulator. The testing was performed at Mars CO2 atmospheric pressure of 7 Torr and consisted of multiple chamber evacuations and backfills. The Programmable Logic Control (PLC) system for the chamber was in the middle of a major overhaul that resulted in utilizing the manual Hand/Off/Auto switches to operate the chamber. Accomplishing this challenging task required the meticulous development of new operating procedures and thorough training of the chamber’s operators.

Ovcharenko, Anton↗
DOE OSTI2019

Operation and Process Control Development for a Pilot-Scale Leaching and Solvent Extraction Circuit Recovering Rare Earth Elements from Coal-Based Sources

The US Department of Energy in 2010 has identified several rare earth elements as critical materials to clean technologies. As part of ongoing research in REEs recovery from coal sources, the University of Kentucky has designed, developed and is demonstrating a ¼ ton/hour pilot-scale processing plant to produce high grade REEs from coal sources. To accomplish process control, PLC systems design/deployment, overall operational design and the utilization of Six Sigma design methodology by the team will be presented. Furthermore, application of the controls design, both procedural and electronic, team’s utilization of data analysis and integration for database decision-making will be discussed.

Leaching↗
DOE OSTI2025

IOTA Pre-Bake Test Development

The IOTA (Integrable Optics Test Accelerator) Bakeout project is intended to improve the quality of the vacuum within the IOTA ring. Impurities consisting of hydrogen and oxygen that build within the beampipe are reduced through applying heat to the beampipe’s exterior. Two versions of the Bakeout project exist, one as a smaller scale test setup, and one five times larger located within the IOTA ring. During my internship, I worked together with a team to bring this project from an effectively dormant state to ready for testing, working together to create full documentation of the PLC (Programmable Logic Controller) programs, making multiple new hardware configurations of this test possible, as well as an additional safety system.

Seagrave, Kayla [DuPage Coll.; Fermilab]↗
DOE OSTI2025

Innovative PLC Design for Optimized Potable Water Managment

My project here at Idaho National Laboratory (INL) was to work on Potable Water PLC Design (Programmable Logic Controllers). I was tasked in making a new panel design for the PLC system that will be moved from TRA BLDG 696 to TRA BLDG 608. This design needed to be updated since the old PLC system being about 20 years old. The manufacturer of the MicroLogix 1200 life expectancy showed it to be 10-20 years, and the system was discontinued in 2017. The new system we implemented was called CompactLogix Controller 5380, along with a new 24 VDC/10 Amp Power Supply. I made a design using Microsoft Visio, with the new material. But we needed to add it onto an Aluminum Panel that the system will be mounted onto, we need Unistrut’s for the aluminum panel to be mounted to. Some of the material we will still be using, like the R1 Alarm Relay, will be moving with the PLC system. The rest of the material will be new supplies that need to be updated systems, which the site is waiting for to complete the PLC system.

47 - OTHER INSTRUMENTATION↗
DOE OSTI2025

From Obsolete to Optimal (ATR Demineralized Water System)

My project was migrating a Human-Machine Interface (HMI) and Programmable Logic Controller (PLC) program from legacy software to a modern platform, enhancing operational efficiency and eliminating unsupported, obsolete equipment. Initially, I used a migration tool to transfer the programs to the new software, then manually updated variables to align with the new PLC. I optimized the PLC code by leveraging new scaling features in the I/O cards, removing over 45 obsolete rungs, and enhancing clarity with functional tag aliases. Next, I modernized the HMI's visuals with an updated color scheme and 3D buttons. I developed multiple interface versions iteratively refining them based on operator feedback. I also designed and created a dedicated "Rounds" screen incorporating insights from a previous intern’s project to streamline daily rounds. To improve clarity, consistency, and efficiency I redesigned the entire interface. Adding visual indicators to enhance operational awareness: red is used for values outside normal specifications, green for normal operating modes, yellow for manual mode, and grey for offline units. Additionally, I added a dynamic visual representation of tank levels, creating PLC logic to show the level in inches as well as inches and feet. I then incorporated a navigation sidebar to facilitate efficient screen transitions. Risk of human error was mitigated by defining narrow input ranges for tank level shutoff and password protecting setpoint changes. I also fixed issues with datatypes that caused inaccuracies in the original code. Overall, this comprehensive upgrade significantly enhanced the HMI's functionality, user experience, and operational reliability.

47 - OTHER INSTRUMENTATION↗
DOE OSTI2025

ON THE EFFECTIVENESS OF LLMS IN UNIT TEST GENERATION FOR STRUCTURED TEXT PROGRAMS

The reliability of industrial automation systems heavily depends on the correctness of Programmable Logic Controller (PLC) programs, which are often written in Structured Text (ST). While Large Language Models (LLMs) have shown promise in automating test generation for mainstream programming languages, their effectiveness for the syntactically strict ST language remains underexplored. This thesis presents a systematic empirical evaluation of three state-of-the-art LLMs—GPT-4o, Gemini 2.5 Pro, and Claude Sonnet 4.5—for generating ST unit tests. We examine three prompting strategies: Natural Language (NL), Code Language (CL), and Chain-of-Thought (CoT), across a curated set of 11 ST function blocks. The quality of the generated tests is assessed using Compilation Success Rate (CSR), Statement Coverage (SC), and Branch Coverage (BC). In the zero-shot setting, Claude Sonnet 4.5 achieves the highest CSR, while Gemini 2.5 Pro consistently delivers the best statement and branch coverage, particularly under CL prompts. By incorporating a one-shot CL prompt, all models exhibit substantial improvements—most notably GPT-4o, whose CSR increases from 45.45% to 90.91%, with substantial gains in both SC and BC. To further contextualize these findings, we compare GPT-4o’s one-shot results with PLCAutoTester, a state-ofthe- art ST unit test generation tool, on an additional benchmark dataset. While LLMgenerated tests approach competitive coverage levels, PLCAutoTester maintains significantly higher and more stable coverage across programs. This study provides the first comprehensive benchmark of modern LLMs for ST unit testing, highlighting their strengths, limitations, and improvements through one-shot prompting, and positioning their performance relative to specialized automated testing tools in industrial automation.

42 ENGINEERING↗
NASA NTRS2001

Adaptive Instrument Module: Space Instrument Controller "Brain" through Programmable Logic Devices

The Adaptive Instrument Module (AIM) will be the first true demonstration of reconfigurable computing with field-programmable gate arrays (FPGAs) in space, enabling the 'brain' of the system to evolve or adapt to changing requirements. In partnership with NASA Goddard Space Flight Center and the Australian Cooperative Research Centre for Satellite Systems (CRC-SS), APL has built the flight version to be flown on the Australian university-class satellite FEDSAT. The AIM provides satellites the flexibility to adapt to changing mission requirements by reconfiguring standardized processing hardware rather than incurring the large costs associated with new builds. This ability to reconfigure the processing in response to changing mission needs leads to true evolveable computing, wherein the instrument 'brain' can learn from new science data in order to perform state-of-the-art data processing. The development of the AIM is significant in its enormous potential to reduce total life-cycle costs for future space exploration missions. The advent of RAM-based FPGAs whose configuration can be changed at any time has enabled the development of the AIM for processing tasks that could not be performed in software. The use of the AIM enables reconfiguration of the FPGA circuitry while the spacecraft is in flight, with many accompanying advantages. The AIM demonstrates the practicalities of using reconfigurable computing hardware devices by conducting a series of designed experiments. These include the demonstration of implementing data compression, data filtering, and communication message processing and inter-experiment data computation. The second generation is the Adaptive Processing Template (ADAPT) which is further described in this paper. The next step forward is to make the hardware itself adaptable and the ADAPT pursues this challenge by developing a reconfigurable module that will be capable of functioning efficiently in various applications. ADAPT will take advantage of radiation tolerant RAM-based field programmable gate array (FPGA) technology to develop a reconfigurable processor that combines the flexibility of a general purpose processor running software with the performance of application specific processing hardware for a variety of high performance computing applications.

Darrin, Ann Garrison↗
NASA NTRS1996

Aqueous-Spray Cleaning System

Simple aqueous-spray cleaning system with overall dimensions comparable to large kitchen refrigerator constructed for use in cleaning hardware in shop. Made of commercially available parts and materials. Incorporates economical cleaner-and-rinse-recycling subsystem, as well as programmable logic-controller device for either manual or automatic operation.

Morgan, Gene E.↗
NASA NTRS1975

The revolution in data gathering systems

This paper gives a review of the data-acquisition systems used in NASA's wind tunnels from the 1950's to the present as a basis for assessing the impact of minicomputers and microcomputers on data acquisition and processing. The operation and disadvantages of wind-tunnel data systems are summarized for the period before 1950, the early 1950's, the early and late 1960's, and the early 1970's. Some significant advances discussed include the use or development of solid-state components, minicomputer systems, large central computers, on-line data processing, autoranging DC amplifiers, MOS-FET multiplexers, MSI and LSI logic, computer-controlled programmable amplifiers, solid-state remote multiplexing, integrated circuits, and microprocessors. The distributed system currently in use with the 40-ft by 80-ft wind tunnel at Ames Research Center is described in detail. The expected employment of distributed systems and microprocessors in the next decade is noted.

Cambra, J. M.↗
NASA NTRS1975

Testability enhancement in digital system design

A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.

Chuang, C. S.↗
NASA NTRS1976

Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

Rickard, D. A.↗
NASA NTRS1981

Army/NASA small turboshaft engine digital controls research program

The emphasis of a program to conduct digital controls research for small turboshaft engines is on engine test evaluation of advanced control logic using a flexible microprocessor based digital control system designed specifically for research on advanced control logic. Control software is stored in programmable memory. New control algorithms may be stored in a floppy disk and loaded directly into memory. This feature facilitates comparative evaluation of different advanced control modes. The central processor in the digital control is an Intel 8086 16 bit microprocessor. Control software is programmed in assembly language. Software checkout is accomplished prior to engine test by connecting the digital control to a real time hybrid computer simulation of the engine. The engine currently installed in the facility has a hydromechanical control modified to allow electrohydraulic fuel metering and VG actuation by the digital control. Simulation results are presented which show that the modern control reduces the transient rotor speed droop caused by unanticipated load changes such as cyclic pitch or wind gust transients.

Sellers, J. F.↗
NASA NTRS2004

Stroboscope Controller for Imaging Helicopter Rotors

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

Jensen, Scott↗
DOE OSTI2022

Programmable soft valves for digital and analog control

In soft devices, complex actuation sequences and precise force control typically require hard electronic valves and microcontrollers. Existing designs for entirely soft pneumatic control systems are capable of either digital or analog operation, but not both, and are limited by speed of actuation, range of pressure, time required for fabrication, or loss of power through pull-down resistors. Using the nonlinear mechanics intrinsic to structures composed of soft materials—in this case, by leveraging membrane inversion and tube kinking—two modular soft components are developed: a piston actuator and a bistable pneumatic switch. These two components combine to create valves capable of analog pressure regulation, simplified digital logic, controlled oscillation, nonvolatile memory storage, linear actuation, and interfacing with human users in both digital and analog formats. Three demonstrations showcase the capabilities of systems constructed from these valves: 1) a wearable glove capable of analog control of a soft artificial robotic hand based on input from a human user’s fingers, 2) a human-controlled cushion matrix designed for use in medical care, and 3) an untethered robot which travels a distance dynamically programmed at the time of operation to retrieve an object. This work illustrates pathways for complementary digital and analog control of soft robots using a unified valve design.

42 ENGINEERING↗
NASA NTRS1981

The Lick Observatory charge-coupled device /CCD/ and controller

A description is given of a flexible microprocessor-based controller for charge-coupled device two-dimensional detectors. It is noted that the controller can operate under manual control or as a slave to a remote computer linked by coaxial cable. The system is discussed, together with data taken at the telescope and in the laboratory. The flexibility of the controller derives from its modular form and from the use of a programmable 8-bit microprocessor to control and sequence the electronic logic. The electronic circuits for such functions as signal processing, clock sequencing, voltage level adjustment, and temperature control are on small individual plug-in cards, making future improvements and changes simple. The software of the microprocessor is stored in erasable, programmable, read-only memory. Among the limitations of the controller is a scan speed of roughly 35 microsec per pixel.

Robinson, L. B.↗
NASA NTRS1988

Implementing neural nets with programmable logic

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Vidal, Jacques J.↗
DOE OSTI2023

Logical quantum processor based on reconfigurable atom arrays

Suppressing errors is the central challenge for useful quantum computing, requiring quantum error correction (QEC) for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays, our system combines high two-qubit gate fidelities, arbitrary connectivity, as well as fully programmable single-qubit rotations and mid-circuit readout. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code distance from d = 3 to d = 7, preparation of colour-code qubits with break-even fidelities, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks, we realize computationally complex sampling circuits with up to 48 logical qubits entangled with hypercube connectivity with 228 logical two-qubit gates and 48 logical CCZ gates. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS2004

Event-Driven Random-Access-Windowing CCD Imaging System

A charge-coupled-device (CCD) based high-speed imaging system, called a realtime, event-driven (RARE) camera, is undergoing development. This camera is capable of readout from multiple subwindows [also known as regions of interest (ROIs)] within the CCD field of view. Both the sizes and the locations of the ROIs can be controlled in real time and can be changed at the camera frame rate. The predecessor of this camera was described in High-Frame-Rate CCD Camera Having Subwindow Capability (NPO- 30564) NASA Tech Briefs, Vol. 26, No. 12 (December 2002), page 26. The architecture of the prior camera requires tight coupling between camera control logic and an external host computer that provides commands for camera operation and processes pixels from the camera. This tight coupling limits the attainable frame rate and functionality of the camera. The design of the present camera loosens this coupling to increase the achievable frame rate and functionality. From a host computer perspective, the readout operation in the prior camera was defined on a per-line basis; in this camera, it is defined on a per-ROI basis. In addition, the camera includes internal timing circuitry. This combination of features enables real-time, event-driven operation for adaptive control of the camera. Hence, this camera is well suited for applications requiring autonomous control of multiple ROIs to track multiple targets moving throughout the CCD field of view. Additionally, by eliminating the need for control intervention by the host computer during the pixel readout, the present design reduces ROI-readout times to attain higher frame rates. This camera (see figure) includes an imager card consisting of a commercial CCD imager and two signal-processor chips. The imager card converts transistor/ transistor-logic (TTL)-level signals from a field programmable gate array (FPGA) controller card. These signals are transmitted to the imager card via a low-voltage differential signaling (LVDS) cable assembly. The FPGA controller card is connected to the host computer via a standard peripheral component interface (PCI).

Monacos, Steve↗