Search NASA⌕ Search

SEARCH · Search NASA

Results for “system on a chip”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS2007

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗
NASA NTRS2012

Dynamically Reconfigurable Systolic Array Accelerator

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Dasu, Aravind↗
NASA NTRS2012

Stereo and IMU-Assisted Visual Odometry for Small Robots

This software performs two functions: (1) taking stereo image pairs as input, it computes stereo disparity maps from them by cross-correlation to achieve 3D (three-dimensional) perception; (2) taking a sequence of stereo image pairs as input, it tracks features in the image sequence to estimate the motion of the cameras between successive image pairs. A real-time stereo vision system with IMU (inertial measurement unit)-assisted visual odometry was implemented on a single 750 MHz/520 MHz OMAP3530 SoC (system on chip) from TI (Texas Instruments). Frame rates of 46 fps (frames per second) were achieved at QVGA (Quarter Video Graphics Array i.e. 320 240), or 8 fps at VGA (Video Graphics Array 640 480) resolutions, while simultaneously tracking up to 200 features, taking full advantage of the OMAP3530's integer DSP (digital signal processor) and floating point ARM processors. This is a substantial advancement over previous work as the stereo implementation produces 146 Mde/s (millions of disparities evaluated per second) in 2.5W, yielding a stereo energy efficiency of 58.8 Mde/J, which is 3.75 better than prior DSP stereo while providing more functionality.

Source record↗
NASA NTRS2020

NASA SpaceCube Intelligent Multi-Purpose System for Enabling Remote Sensing, Communication, and Navigation in Mission Architectures

New, innovative CubeSat mission concepts demand modern capabilities such as artificial intelligence and autonomy, constellation coordination, fault mitigation, and robotic servicing –all of which require vastly more processing resources than legacy systems are capable of providing. Enabling these domains within a scalable, configurable processing architecture is advantageous because it also allows for the flexibility to address varying mission roles, such as a command and data-handling system, a high-performance application processor extension, a guidance and navigation solution, or an instrument/sensor interface. This paper describes the NASA SpaceCube Intelligent Multi-Purpose System (IMPS), which allows mission developers to mix-and-match 1U (10 cm × 10 cm) CubeSat payloads configured for mission-specific needs. The central enabling component of the system architecture to address these concerns is the SpaceCube v3.0 Mini Processor. This single-board computer features the 20nm Xilinx Kintex UltraScale FPGA combined with a radiation-hardened FPGA monitor, and extensive IO to integrate and interconnect varying cards within the system. To unify the re-usable designs within this architecture, the CubeSat Card Standard was developed to guide design of 1U cards. This standard define spinout configurations, mechanical, and electrical specifications for 1U CubeSat cards, allowing the backplane and mechanical enclosure to be easily extended. NASA has developed several cards adhering to the standard (System-on-Chip, power card, etc.), which allows the flexibility to configure a payload from a common catalog of cards.

Advanced Avionics, Hybrid Processing, Data Process↗
NASA NTRS1996

On-board Neural Processor Design for an Intelligent Multi-sensor Microspacecraft

A compact VLSI neural processor based on the Optimization Cellular Neural Network (OCNN)has been under development to provide a wide range of support for an intelligent remote sensing microspacecraft which requires both high bandwidth communication and high-performance computing for on-board data analysis, thematic data reduction, synergy of multiple types of sensors, and other smart-sensor functions. The OCNN architecture is a programmable multi-dimensional array of neurons which are locally connected with their local neurons. The OCNN operation theory, architecture, design and implementation, prototype chip, and system applications have been investigated in detail and presented in this paper.

array↗
NASA NTRSDate not supplied

NOR Flash Memory Scrubbing Application for Boot File Preservation of NASA’s Descent and Landing Computer (DLC)

Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE)project continues, specifically with this development of the Descent and Landing Computer(DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementationof algorithms and operation of sensors to autonomously guide a spacecraft in performing moreprecise and safer landings on celestial bodies such as the Moon and Mars. The second iterationof the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalitiesis the ability to preserve the fidelity of the system’s boot file through the use of memoryscrubbing. The ETU has two primary boards, one for housing a Multi-Processor System ona Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA3. To emulate amemory scrubbing function implemented on the ETU’s FPGA board, the design and testingof a software application was performed on a Xilinx KCU105 FPGA evaluation board. Thememory scrubbing application had to meet certain key criteria such as (1) properly utilize withthe flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memoryproperly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able tocorrect all detected errors, and (4) perform memory scrubbing indefinitely and autonomously.A prototype implementation was constructed and tested, demonstrating successful detectionand correction of bit errors in multiple configurations. In the form of burst errors or singularbit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the applicationwas successful in preserving memory fidelity.

Radiation tolerant↗
NASA NTRS2020

Overview and Status of EXCLAIM, the Experiment for Cryogenic Large-Aperture Intensity Mapping

The EXperiment for Cryogenic Large-Aperture Intensity Mapping (EXCLAIM) is a balloon-borne far-infrared telescope that will survey star formation history over cosmological time scales to improve our un-derstanding of why the star formation rate declined at redshiftz <2, despite continued clustering of darkmatter. Specifically, EXCLAIM will map the emission of redshifted carbon monoxide and singly ionized carbon lines in windows over a redshift range0< z <3.5, following an innovative approach known asintensity mapping. Intensity mapping measures the statistics of brightness fluctuations of cumulative lineemissions, as opposed to detecting individual galaxies, thus enabling a blind, complete census of the emittinggas. To detect this emission unambiguously, EXCLAIM will cross-correlate with a rich spectroscopic galaxycatalog. The EXCLAIM mission will use a cryogenic design to cool the telescope optics to approximately1.7K. The telescope will feature a90-cm primary mirror to probe spatial scales on the sky from the linearregime up to shot-noise-dominated scales. The telescope optical elements will couple to six μ-Spec spectrom-eter modules, operating over a420–540-GHz frequency band with a spectral resolution of512and featuringMicrowave Kinetic Inductance Detectors (MKIDs). In the baseline design, the detectors will be read out witha Radio Frequency System-on-Chip (RFSoC). The cryogenic telescope and the sensitive detectors will allowEXCLAIM to reach high sensitivity in spectral windows of low emission in the upper atmosphere. Here, anoverview of the mission design and development status since the start of the EXCLAIM project in early 2019 is presented.

Giuseppe Cataldo↗
NASA NTRS2006

Catastrophic Fault Recovery with Self-Reconfigurable Chips

Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of 'Self-Reconfigurable Chips' as a last resort effort to 'repair' a faulty critical component.

fault tolerance↗
NASA NTRS2006

Catastrophic fault recovery with self-reconfigurable chips

Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of "Self-Reconfigurable Chips" as a last resort effort to "repair" a faulty critical component.

Chau, Savio N.↗
NASA NTRS2025

System for Long-Duration Electrical Testing of SiC IC Generation 12 Chips at 500 °C

The system described in this report is an improved testing rig designed to enhance measurement flexibility, provide a compact oven footprint, and reduce costs for parallel oven-testing silicon carbide (SiC) integrated circuit devices at 500 °C for long durations (greater than 100 h). The testing rig design was characterized in terms of the ovens’ internal and external temperatures, system noise, and the leakage properties of their substrate/inner boards, where the devices under test (DUTs) reside. The test rig employs a National Instruments (NI) Peripheral Component Interconnect eXtensions for Instrumentation (PXI) measurement system, room-temperature pin-switching/customizing boards, and high-temperature compact ovens.

Stephanie Booth↗
NASA NTRS1990

FEC decoder design optimization for mobile satellite communications

A new telecommunications service for location determination via satellite is being proposed for the continental USA and Europe, which provides users with the capability to find the location of, and communicate from, a moving vehicle to a central hub and vice versa. This communications system is expected to operate in an extremely noisy channel in the presence of fading. In order to achieve high levels of data integrity, it is essential to employ forward error correcting (FEC) encoding and decoding techniques in such mobile satellite systems. A constraint length k = 7 FEC decoder has been implemented in a single chip for such systems. The single chip implementation of the maximum likelihood decoder helps to minimize the cost, size, and power consumption, and improves the bit error rate (BER) performance of the mobile earth terminal (MET).

Roy, Ashim↗
NASA NTRSDate not supplied

Minimally Intrusive Single-Chip Recession/Temperature Sensors for Spacecraft Thermal Protection Systems

We report the initial results of ongoing development of minimally intrusive, single-chip integrated capacitive recession/temperature sensors that would provide real-time monitoring of ablation recession of heatshield thermal protection systems (TPS) during spacecraft atmospheric entry. This work, which was performed using Phenolic Impregnated Carbon Ablator (PICA), is also to demonstrate the ease of sensor insertion during TPS manufacturing, thereby resulting in faster, low-cost, uniform sensor assembly, and spatial distribution, without compromising TPS structural integrity. Using oxy-acetylene flame at 500 W-cm-2 heat flux for 16 seconds, the average recession depth of 3.25 mm was obtained. Some measurement problems were encountered in this first attempt. However, the initial results obtained are in relatively good agreement with published data, and offer promise of future improvement based on lessons learned.

Recession↗
NASA NTRS2011

Performance Comparison of Wireless Sensor Network Standard Protocols in an Aerospace Environment: ISA100.11a and ZigBee

Wireless Sensor Networks (WSNs) can provide a substantial benefit in spacecraft systems, reducing launch weight and providing unprecedented flexibility by allowing instrumentation capabilities to grow and change over time. Achieving data transport reliability on par with that of wired systems, however, can prove extremely challenging in practice. Fortunately, much progress has been made in developing standard WSN radio protocols for applications from non-critical home automation to mission-critical industrial process control. The relative performances of candidate protocols must be compared in representative aerospace environments, however, to determine their suitability for spaceflight applications. In this paper, we will present the results of a rigorous laboratory analysis of the performance of two standards-based, low power, low data rate WSN protocols: ZigBee Pro and ISA100.11a. Both are based on IEEE 802.15.4 and augment that standard's specifications to build complete, multi-hop networking stacks. ZigBee Pro targets primarily the home and office automation markets, providing an ad-hoc protocol that is computationally lightweight and easy to implement in inexpensive system-on-a-chip components. As a result of this simplicity, however, ZigBee Pro can be susceptible to radio frequency (RF) interference. ISA100.11a, on the other hand, targets the industrial process control market, providing a robust, centrally-managed protocol capable of tolerating a significant amount of RF interference. To achieve these gains, a coordinated channel hopping mechanism is employed, which entails a greater computational complexity than ZigBee and requires more sophisticated and costly hardware. To guide future aerospace deployments, we must understand how well these standards relatively perform in analog environments under expected operating conditions. Specifically, we are interested in evaluating goodput -- application level throughput -- in a representative crewed environment in the presence of varying levels of 802.11g Wi-Fi traffic. To do so, we use the NASA Johnson Space Center Wireless Habitat Testbed (WHT), a metallic, habitation-sized module designed for co-existence testing of wireless systems. In its quiescent state, the sealed WHT provides an RF-quiet environment to which we can selectively add interfering systems; it also provides a realistic level of multi-path self-interference for systems under investigation. In our test, we deploy two representative five node networks, configured in a star topology with all nodes reporting directly to a WSN gateway. Each ZigBee network WSN node is built using a Texas Instruments (TI) CC2530 system-on-a-chip radio running TI's ZigBee Pro Z-stack. Each ISA100.11a network node is built using a Nivis VersaNode 210 system-on-a-chip radio. In both cases, radios interface with TI MSP430-F5438 microcontroller implementing a common test application. Interference is provided by a D-link 802.11g Wi-Fi router transporting traffic generated using the Iperf network testing tool. For the single-channel ZigBee network, effects of both direct and indirect Wi-Fi interference are evaluated. For the channel-hopping ISA100.11a network, effects of interference from multiple Wi-Fi routers configured in non-overlapping 802.11g channels are evaluated. Our results show that, in general, the more lightweight ZigBee network performs well at low interference levels, but performance degrades as interference increases. Conversely, the more complex and costly ISA100.11a network continues to perform well as Wi-Fi interference levels increase.

Wagner, Raymond S.↗
NASA NTRSDate not supplied

Developing High-Throughput Organ-on-a-Chip Models to Investigate the Effects of Ionizing Radiation on the Central Nervous System

One of the main health risks in human space exploration is central nervous system (CNS) damage by ionizing radiation due to exposure to the galactic cosmic rays (GCRs). In animal models, irradiation with simulated GCRs or their components has been shown to cause neuronal damage and neuroinflammation associated with cognitive and behavioral dysfunction. In general, the extent of CNS damage is partially regulated by the blood-brain barrier (BBB), which enables immune cells to enter the CNS. The main cellular regulators of BBB permeability are astrocytes, which also modulate neuronal death, immune responses and oxidative stress, and thus could serve as a robust CNS-specific target for countermeasure development. However, studies on BBB permeability and astrocyte functions in regulating CNS responses to ionizing radiation have been limited, especially in human tissue/organ analogs. Therefore, we established a high-throughput 3D organ-on-a-chip system to study human CNS and BBB impairments in response to ionizing radiation, based on commercially available OrganoPlates (Mimetas, Inc.) seeded with primary or induced pluripotent stem cell-derived human cells. We investigated both immediate and delayed CNS responses to major GCR components: 0.15-0.5 Gy 250MeV/n 4-He, and 0.3-0.8 Gy 600 MeV/n 56-Fe; as well as to 0.5-1 Gy X-rays. We observed ionizing radiation-mediated increases in BBB permeability that was exacerbated by astrocyte presence and accompanied by morphological changes in endothelial cells and tight junctions, altered cytokine profile including TNFa upregulation, and increased oxidative stress. We also quantified irradiation-mediated changes in astrocyte activation and neuronal functions, revealing major astrocyte damage mediated by 600MeV/n 56-Fe particles. Thus, we demonstrate that deep space radiation may contribute to CNS damage by disrupting both astrocyte and endothelial cell components of the blood-brain barrier. Our next steps include mapping and validating the transcriptomic changes induced by simulated GCRs and their components in human CNS models. Ultimately, we aim to uncover potential novel targets for countermeasure developments to mitigate CNS damage in long duration spaceflight.

Radiation↗
NASA NTRS1980

Single-chip microcomputer application in high-altitude balloon orientation system

This paper describes the application of a single-chip microcomputer in a high-altitude balloon instrumentation system. The system, consisting of a magnetometer, a stepping motor, a microcomputer and a gray code shaft encoder, is used to provide an orientation reference to point a scientific instrument at an object in space. The single-chip microcomputer, Intel's 8748, consisting of a CPU, program memory, data memory and I/O ports, is used to control the orientation of the system.

Lim, T. S.↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS2019

Developing High-Throughput Organ-On-A-Chip Models to Investigate the Effects of Ionizing Radiation on the Central Nervous System

One of the main health risks in human space exploration is central nervous system (CNS) damage by ionizing radiation. Irradiation with simulated GCRs or their components, or high doses of low-LET radiation such as gamma rays, in animal models has been shown to cause neuronal damage together with glial cell activation and neuroinflammation and has been associated with prolonged cognitive and behavioral dysfunction. The extent of CNS damage in response to any insult, including ionizing radiation, is partially regulated by the blood-brain barrier (BBB), which enables immune cells to enter the CNS. The main cellular regulators of BBB permeability are astrocytes, which also modulate neuronal death, immune responses and oxidative stress, and thus could serve as a robust CNS-specific target for countermeasure development. However, studies on BBB permeability and astrocyte functions in regulating CNS responses to ionizing radiation have been limited, especially in human tissue/organ analogs. Therefore, we have established a high throughput 3D organ-on-a-chip system to study human CNS functions in response to ionizing radiation, with the eventual goal of adapting it to spaceflight missions. We utilized commercially available OrganoPlate system (Mimetas, Inc.) seeded with primary or induced pluripotent stem cell-derived human cells for developing 3D neuronal-astrocytic and BBB models. We investigated both immediate and delayed CNS dose responses to 0.5-1 Gy X-rays by measuring BBB permeability and morphology, and astrocyte activation. We have also quantified secreted markers of oxidative stress and cell viability. In the future, we are planning to monitor dendritic, axonal and synaptic changes in neurons, evaluate the combined exposures to simulated microgravity and ionizing radiation, and compare the responses to low and high-LET ionizing radiation. We anticipate these studies could indicate novel cellular and mechanistic targets for countermeasure developments to improve CNS functions in astronauts.

Malkani, Sherina↗