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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,081 records · Page 60
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Method and apparatus for fast context cloning in a data processing system

A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.

Beard, Jonathan Curtis↗
DOE OSTI2019

Device for controlling additive manufacturing machinery

A computing device for controlling the operation of an additive manufacturing machine comprises a memory element and a processing element. The memory element is configured to store a three-dimensional model of a part to be manufactured, wherein the three-dimensional model defines a plurality of cross sections of the part. The processing element is in communication with the memory element. The processing element is configured to receive the three-dimensional model, determine a path across a surface of each cross section, wherein the path includes a plurality of parallel lines, calculate a power for a radiation beam to scan each of the lines, such that the power varies from line to line non-linearly according to a length of the line, and calculate a scan speed for the radiation beam for each of the lines, such that the scan speed varies line to line non-linearly according to the power of the radiation beam.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Device for controlling additive manufacturing machinery

A computing device for controlling the operation of an additive manufacturing machine comprises a memory element and a processing element. The memory element is configured to store a three-dimensional model of a part to be manufactured, wherein the three-dimensional model defines a plurality of cross sections of the part. The processing element is in communication with the memory element. The processing element is configured to receive the three-dimensional model, determine a plurality of paths, each path including a plurality of parallel lines, determine a radiation beam power for each line, such that the radiation beam power varies non-linearly according to a length of the line, and determine a radiation beam scan speed for each line, such that the radiation beam scan speed is a function of a temperature of a material used to manufacture the part, the length of the line, and the radiation beam power for the line.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Method and apparatus for reordering in a non-uniform compute device

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Method and apparatus for scheduling in a non-uniform compute device

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Dynamic cache bypassing

A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Device and method for detecting presence of a wireless communication device

A device and method for detecting presence of a wireless communication device having an antenna with intrinsic characteristics includes a transmitter, a receiver, a memory element, and a processing element. The transmitter may send a first signal to the antenna of the wireless communication device. The receiver may receive a second signal from the antenna of the wireless communication device, the second signal being a first portion of the first signal that is reflected by the antenna based on intrinsic characteristics of the antenna. The memory element may store intrinsic characteristic information for the antenna. The processing element may determine presence of the wireless communication device by analyzing the second signal against the intrinsic characteristic information stored in the memory element.

Allnutt, Daniel↗
DOE OSTI2020

Device for controlling additive manufacturing machinery

A computing device for controlling the operation of an additive manufacturing machine comprises a memory element and a processing element. The memory element is configured to store a three-dimensional model of a part to be manufactured, wherein the three-dimensional model defines a plurality of cross sections of the part. The processing element is in communication with the memory element. The processing element is configured to receive the three-dimensional model, determine a plurality of paths, each path including a plurality of parallel lines, determine a radiation beam power for each line, such that the radiation beam power varies non-linearly according to a length of the line, and determine a radiation beam scan speed for each line, such that the radiation beam scan speed is a function of a temperature of a material used to manufacture the part, the length of the line, and the radiation beam power for the line.

Barr, Christian↗
DOE OSTI2020

Device for controlling additive manufacturing machinery

A computing device for controlling the operation of an additive manufacturing machine comprises a memory element and a processing element. The memory element is configured to store a three-dimensional model of a part to be manufactured, wherein the three-dimensional model defines a plurality of cross sections of the part. The processing element is in communication with the memory element. The processing element is configured to receive the three-dimensional model, determine a path across a surface of each cross section, wherein the path includes a plurality of parallel lines, calculate a power for a radiation beam to scan each of the lines, such that the power varies from line to line non-linearly according to a length of the line, and calculate a scan speed for the radiation beam for each of the lines, such that the scan speed varies line to line non-linearly according to the power of the radiation beam.

Barr, Christian↗
DOE OSTI2020

Device for controlling additive manufacturing machinery

A computing device for controlling the operation of an additive manufacturing machine comprises a memory element and a processing element. The memory element is configured to store a three-dimensional model of a part to be manufactured, wherein the three-dimensional model defines a plurality of cross sections of the part. The processing element is in communication with the memory element. The processing element is configured to receive the three-dimensional model, determine a plurality of paths, each path including a plurality of parallel lines, determine a radiation beam power for each line, such that the radiation beam power varies non-linearly according to a length of the line, and determine a radiation beam scan speed for each line, such that the radiation beam scan speed is a function of a temperature of a material used to manufacture the part, the length of the line, and the radiation beam power for the line.

Barr, Christian↗
DOE OSTI2021

Interconnect architecture for three-dimensional processing systems

A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.

Jayasena, Nuwan S.↗
DOE OSTI2022

POSTER: Automatic Differentiation of Parallel Loops with Formal Methods

The accompanying poster to this short paper presents a combination of reverse mode AD and formal methods to enable efficient differentiation of (or backpropagation through) shared-memory parallel code. Compared to the state of the art, our approach can more often avoid the need for atomic updates or private data copies during the parallel derivative computation, even in the presence of unstructured or data-dependent data access patterns. This is achieved by gathering information about the memory access patterns from the input program, which is assumed to be correctly parallelized. This information is then used to build a model of assertions in a theorem prover, which can be used to check the safety of shared memory accesses during the parallel derivative computation

Automatic Differentiation↗
DOE OSTI2022

Control flow guided lock address prefetch and filtering

A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

Mashimo, Susumu↗
DOE OSTI2022

Methods, systems, and apparatuses for in-line variably porous surfaces

Variably porous panels and panel assemblies incorporating shape memory alloy components along with methods for actuating the shape memory alloys are disclosed to predictably alter the porosity of a substrate surface, with the shape memory alloy maintained in an orientation relative to the panel that is in-plane with a mold-line of the panel outer surface.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Systems and methods for tensor scheduling

A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.

Meister, Benoit J.↗
DOE OSTI2022

Modernization efforts for the R -Matrix code SAMMY [Abstract]

The R-Matrix code SAMMY is a widely used nuclear data evaluation code focused on the resolved range, which includes corrections for experimental effects. The code is still mostly written in Fortran 77, and uses a memory management system suitable for the time of its initial writing (1984). A modernization effort is under way to bring the code in-line with modern software development practices. A continuous-integration testing framework was added, automating the large existing set of test cases. It is run on every commit. The memory management was updated to current standard practices suitable for modern software analysis tools. The code can be obtained from https://code.ornl.gov/RNSD/SAMMY. The resonance parameters and covariance information are now stored in C++ objects shared by SAMMY and AMPX, the processing code that generates nuclear data libraries for SCALE. This allows for easier maintenance and access to the resonance parameters inside and outside of SAMMY. This feature is already used by accessing and changing parameters in memory in the Bayesian Monte Carlo Evaluation Framework for Cross Sections Nuclear Data and Integral Benchmark Experiments project, Further plans include the switch to the ENDF reading and writing routines in AMPX, as these routines are more robust, easier to maintain, and support more features. Of note here is support for the new GNDS format. Previously it wasn’t easy to share the full covariance matrix for evaluations containing more than one isotope due to limitations on the ENDF format; this is now supported in GNDS. The data are currently available in a binary SAMMY format and can be exported to GNDS to make them more widely available and sharable. The next step will be to use the same resonance processing code at 0K in AMPX and SAMMY as one of the available Reich-Moore R-Matrix formalism. The first step toward this goal is to isolate the reconstruction into a module that takes resonance parameters as its input and does not depend on SAMMY global parameters. This goal has been achieved and it should now be possible to more easily change the resonance formalism and add enhancements as the Phenomenological R-Matrix parameterization of direct, doorway, and compound nuclear reactions discussed elsewhere on this conference. This concerted modernization and enhancement effort provides multiple advantages to the nuclear data community. It will allow parameter optimization using enhanced formalisms, including experimental effects, that better match complex experimental data. Then those evaluated parameters can immediately be passed off to AMPX to be reconstructed with the exact same cross section model and be put into a data library for subsequent testing using SCALE and the Valid Benchmark suite or other suitable benchmark suites.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2022

GPU cache management based on locality type detection

Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.

Zhang, Xianwei↗
DOE OSTI2023

Last-level collective hardware prefetching

A last-level collective hardware prefetcher (LLCHP) is described. The LLCHP is to detect a first off-chip memory access request by a first processor core of a plurality of processor cores. The LLCHP is further to determine, based on the first off-chip memory access request, that first data associated with the first off-chip memory access request is associated with second data of a second processor core of the plurality of processor cores. The LLCHP is further to prefetch the first data and the second data based on the determination.

Michelogiannakis, Georgios↗