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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,153 records · Page 64
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Investigation into Sizing Photovoltaic with Energy Storage for Off-Grid Transactive Scenarios

In this study, a novel sizing methodology was developed for centralized and interconnected operating strategies of transactive microgrids and several variables were investigated including starting month, initial charge of battery, load variability, unit cost of solar panels and energy storage, number of systems, climate, and required reliability to determine their effect on total cost. The centralized strategy improved cost by seven to ten percent compared to the isolated strategy in every case. The interconnected strategy saved an incremental amount of money consistently compared to the isolated standard. The number of connected systems was not a strong effect. It was thought that increasing the number of systems would increase the benefit of energy sharing. Climate zones studied (“Cold”; “Hot-Dry/Mixed Dry”; “Mixed Humid”; and “Cold but with lower solar irradiation”) showed a large variation on cost with the Hot-Dry/Mixed Dry being the least expensive and Cold, with lower solar irradiation being the most expensive. Cost sensitivity analysis was performed showing that the unit cost of solar has a greater effect on the total cost. Required reliability of power, measured in outage hours, exhibited an inverse relation with cost.

14 SOLAR ENERGY↗
DOE OSTI2022

Resilience Design Patterns: A Structured Approach to Resilience at Extreme Scale (V.2.0)

Reliability is a serious concern for future extreme-scale high-performance computing (HPC) systems. Projections based on the current generation of HPC systems and technology roadmaps suggest the prevalence of very high fault rates in future systems. The errors resulting from these faults will propagate and generate various kinds of failures, which may result in outcomes ranging from result corruptions to catastrophic application crashes. Therefore, the resilience challenge for extreme-scale HPC systems requires coordination between various hardware and software technologies that are capable of handling a broad set of fault models at accelerated fault rates. Also, due to practical limits on power consumption in future HPC systems, they are likely to embrace innovative architectures, increasing the levels of hardware and software complexities. Therefore, the techniques that seek to improve resilience must navigate the complex trade-off space between resilience and the overheads to power consumption and performance. While the HPC community has developed various resilience solutions, application-level techniques as well as system-based solutions, the solution space of HPC resilience techniques remains fragmented. There are no formal methods to integrate the various HPC resilience techniques into composite solutions, nor are there methods to holistically evaluate the adequacy and efficacy of such solutions in terms of their protection coverage, and their performance & power efficiency characteristics. Additionally, few implementations of current resilience solutions are portable to newer architectures and software environments that will be deployed on future systems. We developed a new structured approach to the management of HPC resilience using the concept of resilience-based design patterns. In general, a design pattern is a repeatable solution to a commonly occurring problem. We identified the well-known solutions that are commonly used to deal with faults, errors and failures in HPC systems. In the initial design patterns specification (version 1.0), we described the various solutions, which address specific problems in the design of resilient HPC environments, in the form of patterns. Each pattern describes a problem caused by a fault, error or failure event in an HPC environment, and then describes the core of the solution of the problem in such a way that this solution may be adapted to different systems and implemented at different layers of the system stack. The catalog of these resilience design patterns provides designers with a collection of design elements. To construct complete resilience solutions using combinations of various patterns, we defined a framework that enhances HPC designers' understanding of the important constraints and the opportunities for the design patterns to be implemented and deployed at various layers of the system stack. The design framework is also useful for establishing interfaces and mechanisms to coordinate flexible fault management across hardware and software components, as well as to consider the trade-off between performance, resilience, and power consumption when constructing a solution. The resilience design patterns specification version 1.1 included more detailed explanations of the pattern solutions, the context in which the patterns are applicable, and the implications for hardware or software design. It also provided several additional examples and detailed case studies to demonstrate the use of patterns to build realistic solutions. In version 1.2 of the specification document, we have improved the pattern descriptions, including graphical representations of the pattern components. These improvements are largely based on critical comments, feedback and suggestions received from pattern experts and readers of the previous versions of the specification. The pattern classification has been modified to further clarify the relationships between pattern categories. This version of the specification also introduces a pattern language for resilience design patterns. The pattern language presents the patterns in the catalog as a network, revealing the relations among the resilience patterns. The language provides designers with the means to explore alternative techniques for handling a specific fault model that may have different efficiency and complexity characteristics. Using the pattern language also enables the design and implementation of comprehensive resilience solutions as a set of interconnected resilience patterns that can be instantiated across layers of the system stack. The overall goal of this work is to provide hardware and software designers, as well as the users and operators of HPC systems, a systematic methodology for the design and evaluation of resilience technologies in HPC systems that keep scientific applications running to a correct solution in a timely and cost-efficient manner despite frequent faults, errors, and failures of various types. Version 2.0 expands the resilience design pattern classification and catalog to include self-stabilization patterns and reliability, availability and performance models for each structural pattern.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Resilience Design Patterns - A Structured Approach to Resilience at Extreme Scale (version 1.2)

We developed a new structured approach to the management of HPC resilience using the concept of resilience-based design patterns. In general, a design pattern is a repeatable solution to a commonly occurring problem. We identified the well-known solutions that are commonly used to deal with faults, errors and failures in HPC systems. In the initial design patterns specification (version 1.0), we described the various solutions, which address specific problems in the design of resilient HPC environments, in the form of patterns. Each pattern describes a problem caused by a fault, error or failure event in an HPC environment, and then describes the core of the solution of the problem in such a way that this solution may be adapted to different systems and implemented at different layers of the system stack. The catalog of these resilience design patterns provides designers with a collection of design elements. To construct complete resilience solutions using combinations of various patterns, we defined a framework that enhances HPC designers’ understanding of the important constraints and the opportunities for the design patterns to be implemented and deployed at various layers of the system stack. The design framework is also useful for establishing interfaces and mechanisms to coordinate flexible fault management across hardware and software components, as well as to consider the trade-off between performance, resilience, and power consumption when constructing a solution. The resilience design patterns specification version 1.1 included more detailed explanations of the pattern solutions, the context in which the patterns are applicable, and the implications for hardware or software design. It also provided several additional examples and detailed case studies to demonstrate the use of patterns to build realistic solutions. In this version 1.2 of the specification document, we have improved the pattern descriptions, including graphical representations of the pattern components. These improvements are largely based on critical comments, feedback and suggestions received from pattern experts and readers of the previous versions of the specification. The pattern classification has been modified to further clarify the relationships between pattern categories. This version of the specification also introduces a pattern language for resilience design patterns. The pattern language presents the patterns in the catalog as a network, revealing the relations among the resilience patterns. The language provides designers with the means to explore alternative techniques for handling a specific fault model that may have different effciency and complexity characteristics. Using the pattern language also enables the design and implementation of comprehensive resilience solutions as a set of interconnected resilience patterns that can be instantiated across layers of the system stack. The overall goal of this work is to provide hardware and software designers, as well as the users and operators of HPC systems, a systematic methodology for the design and evaluation of resilience technologies in HPC systems that keep scientific applications running to a correct solution in a timely and cost-effcient manner despite frequent faults, errors, and failures of various types.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2007

Scaling and Systems Considerations in Pulsed Inductive Thrusters

Performance scaling in pulsed inductive thrusters is discussed in the context of previous experimental studies and modeling results. Two processes, propellant ionization and acceleration, are interconnected where overall thruster performance and operation are concerned, but they are separated here to gain physical insight into each process and arrive at quantitative criteria that should be met to address or mitigate inherent inductive thruster difficulties. The effects of preionization in lowering the discharge energy requirements relative to a case where no preionization is employed, and in influencing the location of the initial current sheet, are described. The relevant performance scaling parameters for the acceleration stage are reviewed, emphasizing their physical importance and the numerical values required for efficient acceleration. The scaling parameters are then related to the design of the pulsed power train providing current to the acceleration stage. The impact of various choices in pulsed power train and circuit topology selection are reviewed, paying special attention to how these choices mitigate or exacerbate switching, lifetime, and power consumption issues.

Polzin, Kurt A.↗
NASA NTRS2015

Analysis of Advanced Thermoelectric Materials and Their Functional Limits

The world's demand for energy is increasing dramatically, but the best energy conversion systems operate at approximately 30% efficiency. One way to decrease energy loss is in the recovery of waste heat using thermoelectric (TE) generators. A TE generator is device that generates electricity by exploiting heat flow across a thermal gradient. The efficiency of a TE material for power generation and cooling is determined by the dimensionless Figure of Merit (ZT): ZT = S(exp. 2)sigmaT/κ: where S is the Seebeck coefficient, sigma is the electrical conductivity, T is the absolute temperature, and κ is the thermal conductivity. The parameters are not physically independent, but intrinsically coupled since they are a function of the transport properties of electrons. Traditional research on TE materials has focused on synthesizing bulk semiconductor-type materials that have low thermal conductivity and high electrical conductivity affording ZT values of 1. The optimization of the σ/κ ratio is difficult to achieve using current material formats, as these material constants are complementary. Recent areas of research are focusing on using nanostructural artifacts that introduce specific dislocations and boundary conditions that scatter the phonons. This disrupts the physical link between thermal (phonon) and electrical (electron) transport. The result is that κ is decreased without decreasing σ. These material formats give ZT values of up to 2 which represent approximately 18% energy gain from waste heat recovery. The next challenge in developing the next generation of TE materials with superior performance is to tailor the interconnected thermoelectric physical parameters of the material system. In order to approach this problem, the fundamental physics of each parameter S, sigma, and κ need to be physically understood in their context of electron/phonon interaction for the construction of new high ZT thermoelectric devices. Is it possible to overcome the physical limit imposed by of the effect of phonon lattice oscillation and energetic electrons towards thermal conductivity? Is the Seebeck coefficient, based on the difference in voltage over temperature gradient ( deltaV/deltaT), an intrinsic parameter of each material? All these parameters were manipulated using nano-bridge and twin-lattice structural concepts at the NASA Langley Research Center. This talk will review the current trend of TE research to optimize the ZT and discuss about new approaches on increasing ZT within functional limits of each parameter.

Kim, Hyun Jung↗
DOE OSTI2025

Real-Time Testbed for Smart Grid Recloser Controller

The growing need for a low voltage recloser has become apparent due to the rise in requirements for a smart grid. This includes more detailed management of power flow forward (towards load) and backward (towards generation), source synchronization in real time, more indepth fault responses, and the use of green energy. The SEL-651R-2 relay is a device that can manage these needs, especially in fault response and synchronization, and is commonly used in systems called microgrids. Microgrids are distribution level systems that are able to operate separated from the main grid, are typically installed much closer to the load(s), and are fed by distributed energy resources (DERs), such as wind, solar or diesel generators. The SEL-651R-2 is normally used in the field with presets operative settings, but the Western Michigan University (WMU) Center for Interdisciplinary Research on Secure, Efficient and Sustainable Energy Technology (WMU InterEnergy Center) wished to test this device in its range of capabilities for microgrid application. A Hardware-In-the-Loop (HIL) testbed was implemented and used through the Real Time Digital Simulator (RTDS) using the RSCAD software to test the SEL-651R-2's use cases and functions. The testbed includes a microgrid with interconnection to a larger main grid, and the relay is meant to control the recloser at the point of common coupling (PCC) between the main grid and microgrid. The testbed shows how basic protections, reclosing, and synchronization checks function when handling faults that affect both the microgrid and the main grid.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2014

Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformational advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM architectures on Exascale computing systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Executive Summary to PDCI Oscillation Damping Controller Software Documentation

This report serves as the executive summary to the comprehensive document that describes the software, control logic, and operational functions of the Pacific DC Intertie (PDCI) Oscillation Damping Controller. The purpose of the damping controller (DCON) is to mitigate inter-area oscillations in the Western Interconnection (WI) by active improvement of oscillatory mode damping using phasor measurement unit (PMU) feedback to modulate power flow in the PDCI. This report provides the high level descriptions, diagrams, and charts to receive a basic understanding of the organization and structure of the DCON software. This report complements the much longer comprehensive software document, and it does not include any proprietary information as the more comprehensive report does. The level of detail provided by the comprehensive report on the software documentation is intended to assist with the process needed to obtain compliance for North American Electric Reliability Corporation Critical Infrastructure Protection (NERC-CIP) as a Bulk energy system Cyber Asset (BCA) device. That report organizes, summarizes, and presents the charts, figures, and flow diagrams that detail the organization and function of the damping controller software. The PDCI Wide-Area Damping Controller is the result of a collaboration between Sandia National Laboratories (SNL), Bonneville Power Administration (BPA), Montana Tech University (MTU), and the Department of Energy (DOE).

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

FORCE Development Status Update: Vertical Integration and Benchmarking of System Dynamics

Recent efforts to establish effective models for grid energy analysis, especially given the increase in variable renewable energy (VRE) sources and the economic challenges faced by traditional nuclear energy, have generated new technological considerations. One effort to improve the economic viability of nuclear power involves investigating integrated energy systems (IES) which include secondary energy systems that introduce flexibility and secondary market possibilities to existing and perceived future nuclear energy generation technologies. To analyze the technical and economic potential of IES, the Framework for Optimization of Resources and Economics (FORCE) tool suite was developed through a collaboration among national laboratories. Within the FORCE tool suite, the Holistic Energy Resource Optimization Network (HERON) provides algorithms for analyzing the long-term viability of potential IES technologies, while HYBRID provides algorithms and models to achieve high-resolution analysis of coupling physics over a short time period. Continued maturing of the FORCE tool suite requires further interconnections between the various tools in the suite in order to ensure consistent analysis. Analyses performed by applying HYBRID to transient process modeling should be easily harvestable as inputs to HERON analyses. The first item in this status update is a demonstration of an automated data pipeline for loading data from HYBRID into HERON analyses. Application of HYBRID results to HERON, as part of using the FORCE tool suite, relies on robust modeling assumptions for the various models included in HYBRID. The second result of this status update is the benchmarking and validation of cost and operational data, with a particular focus on natural gas energy generators. These generators are benchmarked with a focus on contrasting them with proposed thermal energy storage (TES) technologies.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2019

Nanosystems, Edge Computing, and the Next Generation Computing Systems

It is widely recognized that nanoscience and nanotechnology and their subfields, such as nanophotonics, nanoelectronics, and nanomechanics, have had a tremendous impact on recent advances in sensing, imaging, and communication, with notable developments, including novel transistors and processor architectures. For example, in addition to being supremely fast, optical and photonic components and devices are capable of operating across multiple orders of magnitude length, power, and spectral scales, encompassing the range from macroscopic device sizes and kW energies to atomic domains and single-photon energies. The extreme versatility of the associated electromagnetic phenomena and applications, both classical and quantum, are therefore highly appealing to the rapidly evolving computing and communication realms, where innovations in both hardware and software are necessary to meet the growing speed and memory requirements. Development of all-optical components, photonic chips, interconnects, and processors will bring the speed of light, photon coherence properties, field confinement and enhancement, information-carrying capacity, and the broad spectrum of light into the high-performance computing, the internet of things, and industries related to cloud, fog, and recently edge computing. Conversely, owing to their extraordinary properties, 0D, 1D, and 2D materials are being explored as a physical basis for the next generation of logic components and processors. Carbon nanotubes, for example, have been recently used to create a new processor beyond proof of principle. These developments, in conjunction with neuromorphic and quantum computing, are envisioned to maintain the growth of computing power beyond the projected plateau for silicon technology. We survey the qualitative figures of merit of technologies of current interest for the next generation computing with an emphasis on edge computing.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

INS–Support for Formal Cyber Security Education in Brazil–After Action Report

The adoption of digital technology into Instrumentation and Control (I&C) systems in nuclear facilities fundamentally changes the nature of these systems. Greater interconnectivity of reprogrammable, and functionally interdependent control systems has given rise to the need for computer security consideration in digital I&C Systems. The cyber security of I&C systems presents a growing risk to nuclear facilities and requires the development of educational and research tools to ensure the safety of these facilities. Currently there is a major gap in formal educational offerings on cyber security for these Operational Technology (OT) systems. To provide formal cyber security education resources, DOE’s office of International Nuclear Security (INS) partnered with the University of São Paulo (USP) to develop a training course on the cyber security of nuclear facility I&C systems using the hypothetical Nuclear Power Plant, Asherah.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Evolving Competitive Markets in SAPP: Leveraging Competitive Wholesale Electricity Markets to Drive Renewable Generation Capacity in the Southern African Power Pool (SAPP)

The SADC region has significant natural resource potential to increase renewable energy generation, improve electricity reliability, and support economic development. This research finds an apparent lack of confidence from electricity infrastructure investors in SAPP wholesale electricity markets, which increases risk perception and lowers the likelihood of capital deployment. With respect to free market fundamentals, competitive market obstacles and renewable energy development obstacles are characterized. Stakeholders identified the top obstacles to well-functioning competitive markets as insufficient transmission infrastructure for interconnection and regional movement of electricity, dominance of national single-buyer markets, and lack of or weak nation-state regulatory frameworks. Stakeholders prioritized the top three obstacles for renewable energy development as a lack of viable commercial arrangements for variable renewable energy (VRE) balancing, lack of functional and consistent nation-level regulations, and higher project costs related to reliance on imported equipment. With respect to potential solution options, stakeholders prioritized the development of new cost allocation and finance methods to facilitate new transmission expansion, training to educate new or potential new market entrants on SAPP processes, as well as modeling and analysis of regional SAPP participation benefits disaggregated to the nation-state level. From these perspectives, this research identified strategy options for consideration including transitioning SAPP to a regional transmission operator (RTO) for operation and planning of cross-border transmission facilities and market administration, shifting operations of SAPP member transmission systems to Independent System Operators (ISOs), establishing a regional regulatory authority and enhancing market data transparency. Implementing these reforms is expected to be challenging, but not insurmountable, given the domestic political, legal, and jurisdictional complexities of the SADC region.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2020

Contributions of Solar + Storage to Future Power Needs

The costs of solar photovoltaics (PV) have been dropping in recent years, leading to increasing installations of solar PV systems and growing interest in how the technology will impact the electric grid. Additionally, as battery costs decline, there is increasing interest in understanding the benefits and limitations of battery storage for the grid as well as potential co-benefits of coupling battery storage and photovoltaics. This paper presents recent methodological developments to more accurately represent the value and limitations of coupled PV and battery systems in capacity expansion models. These are demonstrated using the Resource Planning Model (RPM), which co-optimizes capacity investments, transmission investments, and reduced-order dispatch through 2045. We simulate the evolution of the generation and transmission system in the Western Interconnection both with and without a coupled PV and battery technology option under two core scenarios - a baseline scenario and a high renewable penetration scenario - coupled with sensitivities assuming low and mid PV and battery cost projections. We analyze the degree to which a variety of configurations of coupled PV + Battery systems are able to meet future electricity needs, under which system conditions this coupled technology becomes beneficial to the electric grid and identify the displaced technologies when coupled solar and storage is introduced into the model. We find that capturing the benefits of co-locating these systems becomes increasingly important as the penetration of solar PV rises, and that in particular it is important to accurately capture the ability of these technologies to shift energy, provide firm capacity, and reduce expected curtailment.

14 SOLAR ENERGY↗
NASA NTRS2001

Packaging Technology Developed for High-Temperature Silicon Carbide Microsystems

High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as sensors and electronics for space missions to the inner solar system, sensors for in situ combustion and emission monitoring, and electronics for combustion control for aeronautical and automotive engines. However, these devices cannot be used until they can be packaged in appropriate forms for specific applications. Suitable packaging technology for operation temperatures up to 500 C and beyond is not commercially available. Thus, the development of a systematic high-temperature packaging technology for SiC-based microsystems is essential for both in situ testing and commercializing high-temperature SiC sensors and electronics. In response to these needs, researchers at Glenn innovatively designed, fabricated, and assembled a new prototype electronic package for high-temperature electronic microsystems using ceramic substrates (aluminum nitride and aluminum oxide) and gold (Au) thick-film metallization. Packaging components include a ceramic packaging frame, thick-film metallization-based interconnection system, and a low electrical resistance SiC die-attachment scheme. Both the materials and fabrication process of the basic packaging components have been tested with an in-house-fabricated SiC semiconductor test chip in an oxidizing environment at temperatures from room temperature to 500 C for more than 1000 hr. These test results set lifetime records for both high-temperature electronic packaging and high-temperature electronic device testing. As required, the thick-film-based interconnection system demonstrated low (2.5 times of the room-temperature resistance of the Au conductor) and stable (decreased 3 percent in 1500 hr of continuous testing) electrical resistance at 500 C in an oxidizing environment. Also as required, the electrical isolation impedance between printed wires that were not electrically joined by a wire bond remained high (greater than 0.4 GW) at 500 C in air. The attached SiC diode demonstrated low (less than 3.8 W/mm2) and relatively consistent dynamic resistance from room temperature to 500 C. These results indicate that the prototype package and the compatible die-attach scheme meet the initial design standards for high-temperature, low-power, and long-term operation. This technology will be further developed and evaluated, especially with more mechanical tests of each packaging element for operation at higher temperatures and longer lifetimes.

Chen, Liang-Yu↗
DOE OSTI2019

Evaluation of Anomaly Detection for Wide-Area Protection Using Cyber Federation Testbed

Cyber physical security research for smart grid is currently one of the nation's top R&D priorities. The existing vulnerabilities in the legacy grid infrastructure make it particularly susceptible to countless cyber-attacks. There is a growing emphasis towards building interconnected, sophisticated federated testbeds to perform realistic experiments by allowing the integration of geographically-dispersed resources in the dynamic cyber-physical environment. In this paper, we present a cyber (network) based federation testbed to validate the performance of an anomaly detector in context of a Wide Area Protection (WAP) security. Specifically, we have utilized the resources available at the Iowa State University Power Cyber (ISU PCL) Laboratory to emulate the substation and local center networks; and the US Army Research Laboratory (ARL); to emulate the regional control center network. Initially, we describe a hardware-in-the loop based experimental setup for implementing data integrity attacks on an IEEE 39 bus system. We then perform network packet analysis focusing on latency and bandwidth as well as evaluate the performance of a decision tree based anomaly detector in measuring its ability to identify different attacks. Our experimental results reveal the computed wide area network latency; bandwidth requirement for minimum packet loss; and successful performance of the anomaly detector. Our studies also highlight the conceptual architecture necessary for developing the federated testbed, inspired by the NASPI network.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2017

Supplemental Information for New York State Standardized Interconnection Requirements

This document is intended to aid in the understanding and application of the New York State Standardized Interconnection Requirements (SIR) and Application Process for New Distributed Generators 5 MW or Less Connected in Parallel with Utility Distribution Systems, and it aims to provide supplemental information and discussion on selected topics relevant to the SIR. This guide focuses on technical issues that have to date resulted in the majority of utility findings within the context of interconnecting photovoltaic (PV) inverters. This guide provides background on the overall issue and related mitigation measures for selected topics, including substation backfeeding, anti-islanding and considerations for monitoring and controlling distributed energy resources (DER).

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2019

Degradation and Reliability Advancements in Tubular SOFC (Final Report)

The objective of this project is to improve the degradation and reliability of tubular SOFC and develop technologies applicable to stacks scalable to sub-MW system. The Phase II project scope encompasses the cell level technology development listed here and also bundle level degradation verification; 1. Incorporation of an inexpensive on-cell contamination gettering element in each cell to provide protection for cathode against Cr and S; 2. Enhance the electrical contact between Ag current collector and the lanthanum chromite based interconnection layer; 3. Improve the electrolyte layer sintering recipe to reduce the defect density and related anode oxidation problem

03 NATURAL GAS↗