Results for “task programming” — Page 64

NASA NTRS2009

Enhancing Functional Performance using Sensorimotor Adaptability Training Programs

During the acute phase of adaptation to novel gravitational environments, sensorimotor disturbances have the potential to disrupt the ability of astronauts to perform functional tasks. The goal of this project is to develop a sensorimotor adaptability (SA) training program designed to facilitate recovery of functional capabilities when astronauts transition to different gravitational environments. The project conducted a series of studies that investigated the efficacy of treadmill training combined with a variety of sensory challenges designed to increase adaptability including alterations in visual flow, body loading, and support surface stability.

Bloomberg, J. J.↗

NASA NTRS2023

Development of Two High-Energy Bus ‘Cores’ for Rapid Support of Low-TRL and Educational Payloads: A Software-Configured EPS Combined with Flexible C&DH

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Spacecraft↗

NASA NTRSDate not supplied

Development of Two High-Energy Bus ‘Cores’ for Rapid Support of Low-TRL and Educational Payloads: A Software-Configured EPS Combined with Flexible C&DH

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Spacecraft↗

NASA NTRSDate not supplied

Development of Two High-Energy Bus ‘Cores’

For several years the TechEdSat flight series (TES-n), developed by the Nano Orbital Workshop (NOW) group at NASA Ames, has relied upon an in-house developed unit to serve both EPS (Electrical Power System) and C&DH (Command and Data Handling) roles along with low data-rate telemetry functions, i.e., serving as the ‘core’ of the spacecraft bus. This ‘core’ has a considerable task given the rapid cadence of the TES program and the typically low-TRL of payloads; configurability and compatibility are key to prevent mission-specific hardware. However, at only 15 watts the current core has become insufficient to support the program’s growing missions and increasingly demanding payloads. To this end, the NOW program is developing new cores to support two TES mission classes: a single-PCB ‘MiniCore’ designed to support 80-watt missions 6U or smaller in LEO, and a three-PCB, radiation-tolerant ‘StackCore’ designed to support 6U and larger missions over 500 watts in LEO and beyond. The ‘MiniCore’ design consists of three main segments: a processor-agnostic C&DH, a software-configured EPS, and a backup low data-rate radio. The design philosophy was to enable rapid-manufacture in a turbulent supply chain, hence the design consists of COTS parts with a focus on those able to be drop-in replaced with radiation-tolerant versions when demanded by the mission. As a single PC-104 sized circuit board, power density and ease of integration also dominated design, demanding the use of modern features such as single-point USB-C for easy charging and monitoring of the spacecraft on the ground. The ‘MiniCore’ can support 80 watts of load, 140 watt-hours of storage, and over 20 watts of optimized solar generation with extensive power monitoring throughout. The ‘MiniCore’ supports one battery pack, six solar-panels, six loads, five actuators, Iridium SBD, and an internal 802.15.4 network. Additionally, the processor-agnostic design can accept any PJRC Teensy 3.x or Adafruit Feather microcontroller unit to enable processor scaling with mission requirements or environment. It is expected a development unit of this design will be completed before conference. The ‘StackCore’ design consists of three stacked PC-104 sized circuit boards: one dedicated to power generation and storage, one dedicated to power distribution, and one dedicated to C&DH tasks. This delineation is necessary to support the transition from highly integrated ICs to discrete analog circuitry, enabling a primarily analog control power system able to operate without software in a radiation environment with finer monitoring compared to the ‘MiniCore’ design. The planned base architecture supports over 500 watts of load, 250 watt-hours of storage, and over 80 watts of optimized solar generation. The power distribution board allows for the use of daughter cards hosting custom converters or interfaces for payloads, in addition to the software-configured supplies used on the ‘MiniCore’. This core stack will be managed by a Vorago ARM M4 microcontroller and support the same wireless communications as the ‘MiniCore’, with optional integration of a NOW S-band radio and attitude determination sensors for ‘black box’ functionality. It is expected the prototype will still be in development during conference.

Avery Brock↗

NASA NTRS1990

Beyond the Baseline: Proceedings of the Space Station Evolution Symposium: Space Station Freedom - Volume 1, Part 2

This report contains the individual presentations delivered at the Space Station Evolution Symposium in League City, Texas on February 6, 7, 8, 1990. Personnel responsible for Advanced Systems Studies and Advanced Development within the Space Station Freedom Program reported on the results of their work to date. Systems Studies presentations focused on identifying the baseline design provisions (hooks and scars) necessary to enable evolution of the facility to support changing space policy and anticipated user needs. Also emphasized were evolution configuration and operations concepts including on-orbit processing of space transfer vehicles. Advanced Development task managers discussed transitioning advanced technologies to the baseline program, including those near-term technologies which will enhance the safety and productivity of the crew and the reliability of station systems. Special emphasis was placed on applying advanced automation technology to ground and flight systems.

Source record↗

NASA NTRS1995

Major weapon system environmental life-cycle cost estimating for Conservation, Cleanup, Compliance and Pollution Prevention (C3P2)

The Titan 4 Space Launch Vehicle Program is one of many major weapon system programs that have modified acquisition plans and operational procedures to meet new, stringent environmental rules and regulations. The Environmental Protection Agency (EPA) and the Department of Defense (DOD) mandate to reduce the use of ozone depleting chemicals (ODC's) is just one of the regulatory changes that has affected the program. In the last few years, public environmental awareness, coupled with stricter environmental regulations, has created the need for DOD to produce environmental life-cycle cost estimates (ELCCE) for every major weapon system acquisition program. The environmental impact of the weapon system must be assessed and budgeted, considering all costs, from cradle to grave. The Office of the Secretary of Defense (OSD) has proposed that organizations consider Conservation, Cleanup, Compliance and Pollution Prevention (C(sup 3)P(sup 2)) issues associated with each acquisition program to assess life-cycle impacts and costs. The Air Force selected the Titan 4 system as the pilot program for estimating life-cycle environmental costs. The estimating task required participants to develop an ELCCE methodology, collect data to test the methodology and produce a credible cost estimate within the DOD C(sup 3)P(sup 2) definition. The estimating methodology included using the Program Office weapon system description and work breakdown structure together with operational site and manufacturing plant visits to identify environmental cost drivers. The results of the Titan IV ELCCE process are discussed and expanded to demonstrate how they can be applied to satisfy any life-cycle environmental cost estimating requirement.

Hammond, Wesley↗

NASA NTRS1987

Kinematically redundant robot manipulators

Research on control, design and programming of kinematically redundant robot manipulators (KRRM) is discussed. These are devices in which there are more joint space degrees of freedom than are required to achieve every position and orientation of the end-effector necessary for a given task in a given workspace. The technological developments described here deal with: kinematic programming techniques for automatically generating joint-space trajectories to execute prescribed tasks; control of redundant manipulators to optimize dynamic criteria (e.g., applications of forces and moments at the end-effector that optimally distribute the loading of actuators); and design of KRRMs to optimize functionality in congested work environments or to achieve other goals unattainable with non-redundant manipulators. Kinematic programming techniques are discussed, which show that some pseudo-inverse techniques that have been proposed for redundant manipulator control fail to achieve the goals of avoiding kinematic singularities and also generating closed joint-space paths corresponding to close paths of the end effector in the workspace. The extended Jacobian is proposed as an alternative to pseudo-inverse techniques.

Baillieul, J.↗

DOE OSTI2017

Traleika Glacier: A hardware-software co-designed approach to exascale computing

The move from current petascale machines to future exascale machines will need both hardware improvements and software changes. Hardware will need to evolve to focus primarily on features that lower energy consumption: near-threshold voltage operation, fine-grained power and clock management and heterogeneity. Software will also need to evolve and be able to express more parallelism, become more dynamic and adaptable in order to be able to operate on a much more variable hardware. Here, we present Traleika Glacier, an effort that seeks to evaluate radical design changes to meet the constraints, both in terms of power and cost, of exascale computing. The salient features of the hardware design presented in the work include a) a use of heterogeneous cores, b) a redesign of the memory system that centers around hierarchical scratchpads and a global address space, c) the hardware acceleration of certain memory and network operations through specialized engines and, d) very fine-grained control and monitoring capabilities. On the software side, we describe a task-based runtime system, the Open Community Runtime (OCR) which aims to express a wide range of higher-level programming models with a very limited set of core concepts: event-driven tasks for computation, events for synchronization and relocatable data-blocks for data management.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

ASCENDS: Advanced data SCiENce toolkit for Non-Data Scientists

Recently, advances in machine learning and artificial intelligence have been playing more and more critical roles in a wide range of areas. For the last several years, industries have shown that how learning from data, identifying patterns and making decisions with minimal human intervention can be extremely useful to their business (e.g., image classification, recommending a product to a customer, finding friends in a social network, predicting customers actions, etc.). These success stories have been motivating scientists who study physics, chemistry, materials, medicine, and many other subjects, to explore a new pathway of utilizing machine learning techniques like regression and classification for their scientific activities. However, most existing machine learning tools, systems, and methodologies have been developed for programming experts but not for scientists (or any users) who have no or little knowledge of programming. ASCENDS is a toolkit that is developed to assist scientists (or any persons) who want to use their data for machine learning tasks, more specifically, correlation analysis, regression, and classification. ASCENDS does not require programming skills. Instead, it provides a set of simple but powerful CLI (Command Line Interface) and GUI (Graphic User Interface) tools for non-data scientists to be able to intuitively perform advanced data analysis and machine learning techniques. ASCENDS has been implemented by wrapping around opensource software including Keras, TensorFlow, and scikit-learn.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1996

Technology readiness levels and technology status for selected long term/high payoff technologies on the RLV program

The development of a new space transportation system in a climate of constant budget cuts and staff reductions can be and is a difficult task. It is no secret that NASA's current launching system consumes a very large portion of NASA funding and requires a large army of people to operate & maintain the system. The new Reusable Launch Vehicle (RLV) project and it's programs are faced with a monumental task of making the cost of access to space dramatically lower and more efficient than NASA's current system. With pressures from congressional budget cutters and also increased competition and loss of market share from international agencies RLV's first priority is to develop a 'low-cost, reliable transportation to earth orbit.' One of the RLV's major focus in achieving low-cost, reliable transportation to earth orbit is to rely on the maturing of advanced technologies. The technologies for the RLV are numerous and varied. Trying to assess their current status, within the RLV development program is paramount. There are several ways to assess these technologies. One way is through the use of Technology Readiness Levels (TRL's). This project focused on establishing current (summer 95) 'worst case' TRL's for six selected technologies that are under consideration for use within the RLV program. The six technologies evaluated were Concurrent Engineering, Embedded Sensor Technology, Rapid Prototyping, Friction Stir Welding, Thermal Spray Coatings, and VPPA Welding.

Rosmait, Russell L.↗

NASA NTRS2004

What Multilevel Parallel Programs do when you are not Watching: A Performance Analysis Case Study Comparing MPI/OpenMP, MLP, and Nested OpenMP

With the current trend in parallel computer architectures towards clusters of shared memory symmetric multi-processors, parallel programming techniques have evolved that support parallelism beyond a single level. When comparing the performance of applications based on different programming paradigms, it is important to differentiate between the influence of the programming model itself and other factors, such as implementation specific behavior of the operating system (OS) or architectural issues. Rewriting-a large scientific application in order to employ a new programming paradigms is usually a time consuming and error prone task. Before embarking on such an endeavor it is important to determine that there is really a gain that would not be possible with the current implementation. A detailed performance analysis is crucial to clarify these issues. The multilevel programming paradigms considered in this study are hybrid MPI/OpenMP, MLP, and nested OpenMP. The hybrid MPI/OpenMP approach is based on using MPI [7] for the coarse grained parallelization and OpenMP [9] for fine grained loop level parallelism. The MPI programming paradigm assumes a private address space for each process. Data is transferred by explicitly exchanging messages via calls to the MPI library. This model was originally designed for distributed memory architectures but is also suitable for shared memory systems. The second paradigm under consideration is MLP which was developed by Taft. The approach is similar to MPi/OpenMP, using a mix of coarse grain process level parallelization and loop level OpenMP parallelization. As it is the case with MPI, a private address space is assumed for each process. The MLP approach was developed for ccNUMA architectures and explicitly takes advantage of the availability of shared memory. A shared memory arena which is accessible by all processes is required. Communication is done by reading from and writing to the shared memory.

Jost, Gabriele↗

NASA NTRS1990

Shuttle extravehicular mobility unit (EMU) operational enhancements

An EMU program activity is considered aimed at achieving a 25 percent reduction in ground turnaround man-hours and processing time between missions and extending EVA on-orbit capabilities. Tasks being implemented with expected benefits to NASA-manned spaceflight programs are identified and described. It is concluded that the EMU enhancements made to increase durability and reduce ground processing time will also provide the capability for on-orbit suit resizing and make possible the extension of the present on-orbit certification limit from 3 to 5 EVAs.

Balinskas, Robert↗

NASA NTRS1976

Georgia Institute of Technology research on the Gas Core Actinide Transmutation Reactor (GCATR)

The program reviewed is a study of the feasibility, design, and optimization of the GCATR. The program is designed to take advantage of initial results and to continue work carried out on the Gas Core Breeder Reactor. The program complements NASA's program of developing UF6 fueled cavity reactors for power, nuclear pumped lasers, and other advanced technology applications. The program comprises: (1) General Studies--Parametric survey calculations performed to examine the effects of reactor spectrum and flux level on the actinide transmutation for GCATR conditions. The sensitivity of the results to neutron cross sections are to be assessed. Specifically, the parametric calculations of the actinide transmutation are to include the mass, isotope composition, fission and capture rates, reactivity effects, and neutron activity of recycled actinides. (2) GCATR Design Studies--This task is a major thrust of the proposed research program. Several subtasks are considered: optimization criteria studies of the blanket and fuel reprocessing, the actinide insertion and recirculation system, and the system integration. A brief review of the background of the GCATR and ongoing research is presented.

Clement, J. D.↗

DOE OSTI2024

BAD2matrix: Phylogenomic matrix concatenation, indel coding, and more

Common steps in phylogenomic matrix production include biological sequence concatenation, morphological data concatenation, insertion/deletion (indel) coding, gene content (presence/absence) coding, removing uninformative characters for parsimony analysis, recording with reduced amino acid alphabets, and occupancy filtering. Existing software does not accomplish these tasks on a phylogenomic scale using a single program. BAD2matrix is a Python script that performs the above-mentioned steps in phylogenomic matrix construction for DNA or amino acid sequences as well as morphological data. The script works in UNIX-like environments (e.g., LINUX, MacOS, Windows Subsystem for LINUX).

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2016

Streamlining resummed QCD calculations using Monte Carlo integration

Some of the most arduous and error-prone aspects of precision resummed calculations are related to the partonic hard process, having nothing to do with the resummation. In particular, interfacing to parton-distribution functions, combining various channels, and performing the phase space integration can be limiting factors in completing calculations. Conveniently, however, most of these tasks are already automated in many Monte Carlo programs, such as MadGraph [1], Alpgen [2] or Sherpa [3]. In this paper, we show how such programs can be used to produce distributions of partonic kinematics with associated color structures representing the hard factor in a resummed distribution. These distributions can then be used to weight convolutions of jet, soft and beam functions producing a complete resummed calculation. In fact, only around 1000 unweighted events are necessary to produce precise distributions. A number of examples and checks are provided, including e + e – two- and four-jet event shapes, n -jettiness and jet-mass related observables at hadron colliders at next-to-leading-log (NLL) matched to leading order (LO). Furthermore, the attached code can be used to modify MadGraph to export the relevant LO hard functions and color structures for arbitrary processes.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2016

Enhanced working memory performance via transcranial direct current stimulation: The possibility of near and far transfer

Although working memory (WM) training programs consistently result in improvement on the trained task, benefit is typically short-lived and extends only to tasks very similar to the trained task (i.e., near transfer). It is possible that pairing repeated performance of a WM task with brain stimulation encourages plasticity in brain networks involved in WM task performance, thereby improving the training benefit. In the current study, transcranial direct current stimulation (tDCS) was paired with performance of a WM task (n-back). In Experiment 1, participants performed a spatial location-monitoring n-back during stimulation, while Experiment 2 used a verbal identity-monitoring n-back. In each experiment, participants received either active (2.0 mA) or sham (0.1 mA) stimulation with the anode placed over either the right or the left dorsolateral prefrontal cortex (DLPFC) and the cathode placed extracephalically. In Experiment 1, only participants receiving active stimulation with the anode placed over the right DLPFC showed marginal improvement on the trained spatial n-back, which did not extend to a near transfer (verbal n-back) or far transfer task (a matrix-reasoning task designed to measure fluid intelligence). Here, in Experiment 2, both left and right anode placements led to improvement, and right DLPFC stimulation resulted in numerical (though not sham-adjusted) improvement on the near transfer (spatial n-back) and far transfer (fluid intelligence) task. Results suggest that WM training paired with brain stimulation may result in cognitive enhancement that transfers to performance on other tasks, depending on the combination of training task and tDCS parameters used.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2020

Benchmarking noise extrapolation with the OpenPulse control framework

Distilling precise estimates from noisy intermediate scale quantum (NISQ) data has recently attracted considerable attention Kandala et al., Nature (London) 567, 491 (2019). In order to augment digital qubit metrics, such as gate fidelity, we discuss analog error mitigability, i.e., the ability to accurately distill precise observable estimates, as a hybrid quantum classical computing benchmarking task. Specifically, using Rabi oscillations as a test program, we characterize single qubit error rates on IBM's Poughkeepsie superconducting quantum hardware, incorporate control-mediated noise dependence into a generalized rescaling protocol, and analyze how noise characteristics influence Richardson extrapolation-based error mitigation. Finally, our results identify regions in the space of Hamiltonian control fields and circuit depth which are most amenable to reliable noise extrapolation, as well as shed light on how low-level hardware characterization can be used as a predictive tool for uncertainty quantification in error-mitigated NISQ computations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

IRIS: A Performance-Portable Framework for Cross-Platform Heterogeneous Computing

From edge to exascale, computer architectures are becoming more heterogeneous and complex. The systems typically have fat nodes, with multicore CPUs and multiple hardware accelerators such as GPUs, FPGAs, and DSPs. This complexity is causing a crisis in programming systems and performance portability. Several programming systems are working to address these challenges, but the increasing architectural diversity is forcing software stacks and applications to be specialized for each architecture. As we show, all of these approaches critically depend on their software framework for discovery, execution, scheduling, and data orchestration. To address this challenge, we believe that a more agile and proactive software framework is essential to increase performance portability and improve user productivity. To this end, we have designed and implemented IRIS: a performance-portable framework for cross-platform heterogeneous computing. IRIS can discover available resources, manage multiple diverse programming platforms (e.g., CUDA, Hexagon, HIP, Level Zero, OpenCL, OpenMP) simultaneously in the same execution, respect data dependencies, orchestrate data movement proactively, and provide for user-configurable scheduling. To simplify data movement, IRIS introduces a shared virtual device memory with relaxed consistency among different heterogeneous devices. IRIS also adds an automatic kernel workload partitioning technique using the polyhedral model so that it can resize kernels for a wide range of devices. Our evaluation on three architectures, ranging from Qualcomm Snapdragon to a Summit supercomputer node, shows that IRIS improves portability across a wide range of diverse heterogeneous architectures with negligible overhead.

97 MATHEMATICS AND COMPUTING↗