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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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1,168 records · Page 65
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Development of a Hybrid Single/Two-Phase Capillary-Based Micro-Cooler Using Copper Inverse Opals Wick with Silicon 3D Manifold for High-Heat-Flux Cooling Application: Preprint

Previously, two-phase capillary-based cooling from narrow (200-1,000 micrometer) heater-bridge copper inverse opal (CIO) wicks with heat flux levels exceeding 1,400 watts per square cm with a low superheat of approximately 10 degrees C was demonstrated. Here, we demonstrate the area scaling of the proposed technology to large-area micro-cooler for the high-heat-flux cooling of microprocessors and power electronics. We developed a hybrid single/two-phase micro-cooler that relies on capillary wicking in 25-micrometer-thick CIOs with an open channel silicon 3D-manifold for liquid delivery and vapor extraction, to achieve a high heat flux of approximately 400 watts per square cm over a heated area of 1 square cm. For the range of inlet water (21 degrees C water temperature) flowrates from 5 to 60 mL per min, we achieved total thermal resistances and vapor qualities of 0.68-0.2 square cm Kelvin per watt and 0.55-0.12, respectively. The high heat flux levels are achieved with flowrates that are 10 times smaller than conventional single- or two-phase microchannel cooling technology. The corresponding two-phase thermal resistances are in the range of 0.05 to 0.02 square cm Kelvin per watt with temperature superheat of 8 to 6 degrees C. While the overall performance of the large-area (10 by 10 square millimeter) capillary-based micro-cooler degraded compared to previous demonstration of the technology for a heated area of 5 by 5 square millimeter, preliminary computational fluid dynamics (CFD) modeling indicates that an improved manifold design will be able to achieve comparable performance.

capillary flow↗
DOE OSTI2024

Field Programmable Gate Array Data Capture for Control Systems

Some Industrial Control Systems (ICS) networks are based on protocols such as Serial and Industrial Ethernet. These protocols currently have no existing cybersecurity monitoring tools, leaving a large gap in the cyber defense of critical infrastructure. In order to analyze such ICS traffic, it is first necessary to implement methods of capturing the ICS data. Whereas traditional methods of analyzing data would use microprocessors, the nature of high-speed analog data can be difficult to implement on such a versatile processor, as they are rather inefficient for doing a single task. Whereas Field Programmable Gate Arrays (FPGAs) provide an adequate tool in analyzing high speed data, as despite the lack of program versatility, Programmable Logic can implement a solution with minimal clock cycles, allowing time for each new packet of data to be captured before a new data sample is taken.

42 ENGINEERING↗
NASA NTRS2012

Initial SEE Testing of Maestro

We have reported on initial SEE sensitivity of the full 49-core Maestro device. Supporting the low-level structures and qualitative system observation goals of phase 1 of testing. Observed sensitivities found to be consistent with Boeing predictions. Highlighted by the L1 data cache sensitivity which drives the rates on the current Maestro device. Presented details to the hardware and software setups that show where the limitations - highlighting future work. Key future work includes testing with memory and IO ports.

cache sensitivity↗
NASA NTRS1984

The Development of an Airborne Instrumentation Computer System for Flight Test

Instrumentation interfacing frequently requires the linking of intelligent systems together, as well as requiring the link itself to be intelligent. The airborne instrumentation computer system (AICS) was developed to address this requirement. Its small size, approximately 254 by 133 by 140 mm (10 by 51/4 by 51/2 in), standard bus, and modular board configuration give it the ability to solve instrumentation interfacing and computation problems without forcing a redesign of the entire unit. This system has been used on the F-15 aircraft digital electronic engine control (DEEC) and its follow on engine model derivative (EMD) project and in an OV-1C Mohawk aircraft stall speed warning system. The AICS is presently undergoing configuration for use on an F-104 pace aircraft and on the advanced fighter technology integration (AFTI) F-111 aircraft.

Voice synthesizer↗
NASA NTRS1997

Case Study of the Design of a Viterbi Decoder

This paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.

Viterbi decoder ASIC microprocessor design↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

14nm↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

microprocessor↗
NASA NTRS2020

NEPP Processor Enclave: Testing Artificial Intelligence & Machine Learning

Computational device families are converging and multiple EEE components are required for a complete HPC subsystem. The components of this “processor enclave” are sensitive to radiation effects and therefore must be characterized for mission assurance. NEPP’s standardized approach to testing the Processor Enclave includes math, graphics, and AI and Machine Learning test vectors and device hardware capable of these applications.

Radiation testing↗
NASA NTRS2002

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗
NASA NTRS2000

In-flight observations of multiple-bit upset in DRAMs

In-flight data is examined showing a very high incidence of multiple-bit errors in a solid-state recorder that incorporates error detection and correction. The high MBU rate is shown to be a consequence of the physical selection of memory cell locations in the recorder architecture.

single↗