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In this presentation, we provide a brief glimpse at preliminary single event test results taken from two years of testing of the Xilinx V5QV Field Programmable Gate Array (FPGA). This presentation includes an overview of test philosophy and implementation.
Flight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.
This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.
It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.
We propose a method for TMR insertion verification that satisfies the process for reliable and trusted systems. If a system is expected to be protected using TMR, improper insertion can jeopardize the reliability and security of the system. Due to the complexity of the verification process, there are currently no available techniques that can provide complete and reliable confirmation of TMR insertion. This manuscript addresses the challenge of confirming that TMR has been inserted without corruption of functionality and with correct application of the expected TMR topology. The proposed verification method combines the usage of existing formal analysis tools with a novel search-detect-and-verify tool. Field programmable gate array (FPGA),Triple Modular Redundancy (TMR),Verification, Trust, Reliability,
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4 field programmable gate array (FPGA).
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4 field programmable gate array (FPGA).
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4 field programmable gate array (FPGA).
It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.
It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.
For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.
We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)
The Launch Control System (LCS) is a part of the system used to launch the Space Launch System (SLS). It monitors and control of both vehicle and ground systems for SLS. My internship this spring was focused both on the hardware and software aspects of the command and control system. During my internship I worked in two groups, the Record and Playback Subsystem (RPS) and Kennedy Ground Control Subsystems (KGCS). During my time on RPS, I worked on automating the updating of displays and engineering reports. While on KGCS I worked on creating a power distribution diagram of the Control System Development Lab (CDL) and a new trainer for new interns or employees to gain an understanding of Programmable Logic Controllers (PLCs).
This paper discusses the design and implementation of a miniaturized electronic system for the Planetary Integrated Camera-Spectrometer (PICS). The PICS electronics demonstrates the application of Field Programmable Gate Arrays (FPGAs) and of analog hybrid technology to space flight multispectral systems. A discussion of the electronic system design illustrates how a multisensor instrument consisting of an UV CCD, two visible CCDs, and a near-IR focal plane assembly can be processed through a common set of electronics. Following the system design discussion, the actual electronic design will be presented. Each miniaturized module will be discussed as to functionality and performance. The test setup for bench checkout of a cooled CCD and an IR FPA, including results with breadboard electronics and with the hybrids are also described.
A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.
Multifunctional textiles with programmable, multi-axial, distributed, and scalable actuation are highly desirable and presently unrealized. 1D torque-unbalanced active yarns within 2D textile structures are exploited to produce soft and scalable active textiles that exhibit tunable displacements, forces, stiffnesses, and kinematic deformations. Through a textile hierarchy spanning active material composition, yarn construction, textile geometry, and system architecture, these active textiles accomplish kinetic tunability, variable recruitment behaviors, and auxetic effects without mechanical contact, called active auxetic effects. New modes of pre-programmed multi-axial performance are enabled by geometrically manipulating—specifically pre-stressing and constraining—active filaments in torsion and leveraging their structural elastic instability within a textile geometry. The new kinematic motion afforded by torque-unbalanced active yarns enhances the performance of active textiles, which accomplish tensile strokes over 40%, generated blocked forces up to 308 N m−1, and specific work over 0.4. kJ kg−1. Advances in active textiles are demonstrated through multifunctional 3D applications, including a variable constriction pump that exhibits sequential actuation, a wearable that conforms multi-axially around the body, and a soft exoskeleton that performs assistive motions and on-body anchoring simultaneously. By harnessing the capabilities of active materials within a textile hierarchy, advances in the potentiality of multifunctional textiles are presented.
We present the Programme for Monitoring of the Greenland Ice Sheet (PROMICE) ice velocity product, which is a time series of ice velocity mosaics derived using offset tracking on Sentinel-1 SAR data. The time series starting in January 2016 is continuously updated with a new mosaic every 12 days and is posted at 500 m grid resolution. Within PROMICE, the ice velocity product is used directly as input to estimate the solid ice discharge from the Greenland Ice Sheet as well as to study ice dynamic processes on seasonal and multi-annual time scales. Recently, we have made changes to the processing chain due to spurious cases of slow down detected in a few glaciers in Southeast Greenland. In this contribution, we discuss how this was resolved as well as other recent improvements to the product.
Verification of Programmable Logic Controller (PLC) programs requires reasoning about propositions qualified in terms of time. CERN’s PLCverif, an open-source tool for the analysis of safety-critical PLC systems, uses Linear Temporal Logic (LTL) for the specification of properties. Until now, PLCverif depended on third-party tools that accept LTL specifications to perform verification. However, our experience with industrial PLC programs shows that, to overcome analysis limitations, a wide range of techniques are needed to successfully verify complex properties. In this paper, we extend PLCverif to enable PLC program verification of pure-past LTL (PLTL) safety properties with assertion-based verification tools. To this end, we take an algorithm from the runtime-monitoring domain, apply it to bounded model checking of PLC programs, and implement it in PLCverif. We extend the integration of NASA’s Formal Requirements Elicitation Tool (FRET) into PLCverif to use PLTL properties generated with FRET. In addition, we leverage the program structure induced by the PLC scan-cycle for a state-space reduction. Finally, we expose the algorithm to a real-world case study of critical systems at CERN.