High Energy Micron Scale Pixel Hybrid Detector
The objective of this technology development project has been to fabricate and characterize a new X-ray area image sensor innovation designed for high efficiency detection and imaging of hard X-rays (>20 KeV) with micron scale pixel resolution. A key technology component consists of a monolithic hybrid X-ray detector built by layering an amorphous Selenium X-ray photoconductor film directly deposited on a small pitch (7.8μm) CMOS active pixel readout array. A specific goal of this work is to provide a new detector tool to researchers working with synchrotron light sources, to extend the depth of exploration into nanoscale structures, and do so cost effectively. Early generation X-ray imaging detector tools fail to provide adequate resolving power and efficiency at high energies and our innovation provides a solution. A majority of proposed phase I tasks were completed. Those tasks included, in collaboration with KA Imaging, successful fabrication of specified a-Se layers on a 1Mpixel CMOS readout array to create the direct hybrid X-ray imaging array, packaging of the imaging array, assembly of electronics into a shielded detector box, loading user interface software for camera control and image capture, and performing initial (no X-ray) detector evaluation at Farrier Microengineering facilities. After initial tests, extensive testing using the X-ray beam line 1-BM source at Argonne National Laboratory Advanced Photon Source(ANL-APS) was performed. Imaging performance studies were conducted at multiple X-ray beam energies. Studies included X-ray response vs. X-ray energy, vs. applied detector field strength (HV), response linearity vs. integration time, MTF vs. beam energy, image lag measurements, and micron scale resolution pattern target imaging. This high energy micron scale X-ray detection technology is a first of a kind to be evaluated at the ANL-APS and is supported by Dr. Antonino Miceli, head of the detector physics group. Accomplishments include the first successful demonstration of a 1Mpix amorphous Selenium on CMOS readout direct hybrid X-ray imaging detector at a DOE sponsored National Laboratory. Modeled performance predictions were confirmed, proving micron scale resolution as well as an order of magnitude increase in conversion efficiency over conventional scintillator detector performance. A discovery of evidence of propagation-based phase contrast edge enhancement was unplanned and will be exploited in future experiments. This phase 1 technology demonstration verifies the efficacy of proposed high energy micron scale pixel X-ray hybrid a-Se imaging array products. The new detector products will cost effectively replace early generation detector technologies that currently fail to address increasing demand for tools to study nano structures and physical processes at high X-ray energies above 20keV. For example, current systems for transmission X-ray microscopy have low efficiency and available large pixel (~55µm) direct detectors do not offer sufficient resolution for Bragg fringe imaging at high energies. This detector innovation will solve these inadequacies. The new detector technology will compete in a $50M scientific X-ray detector market, growing at 6%, and will benefit Microtomography(µCT), X-ray diffractometry (XRD), Coherent Diffraction Imaging (CDI) applications. One application specified by Dr. Miceli at ANL is the 3D reconstruction of compact crystals at high energies requires small pixel high efficiency X-ray detectors. Farrier Microengineering, working with colleagues at KA Imaging and the University of Waterloo, successfully achieved the critical objectives of the Phase I proposal. We have proven the technical feasibility of this innovation by building and successfully testing a 1Mpixel a-Se/CMOS hybrid direct X-ray imaging array. Our commercialization roadmap of detector products will be implemented during a phase II project. We will demonstrate a migration of the technology to larger detector array sizes, improved temporal performance with detector layer engineering, and improved environmental and operational stability. Manufacturability and cost effectiveness are key objectives and product designs will leverage current state of the art CMOS wafer fabrication quality and volume manufacturing economics.