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Enabling pulse shape discrimination with commercial ASICs
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ALCOR: A mixed-signal ASIC for the dRICH detector of the ePIC experiment at the EIC
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A Multi-Functional Streaming Readout ASIC With Channel-Embedded DSP and Neural Inference
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ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment
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The VMM3a ASIC
The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.
Achieving High Performance Using Low Tech: Topics and Examples on FPGA and ASIC TDC
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Design of a reconfigurable autoencoder algorithm for detector front-end ASICs
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Design and first test results of the CMS HGCAL on-detector ECON-T ASIC with a reconfigurable encoder algorithm for data compression [Poster]
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The COLDATA Concentrator ASIC for the Deep Underground Neutrino Experiment [Poster]
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MIDNA: Sub-electron skipper-CCD readout with multichannel cryogenic low-noise readout ASICs
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Performance and automatic calibration scheme of the waveform sampler in the ETROC2 ASIC chip
The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge injection test data. After calibration, the baseline random error is reduced by a factor of 2.5–3 compared to the default calibration, and a 5% charge measurement precision is achieved in 15 fC charge injection tests.
Multi-Channel SiPM Readout ASIC with Digital Interface
Presenting project which is under development jointly with LBL
Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)
Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.
True Random Number Generator with Theory-Backed Entropy Rates for ASICs
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Design of a Multiple-Output Voltage Generator PCB for a Comprehensive Verification of the PSEC6, a 1-ps Resolution Mixed-Signal ASIC
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Triple-Error-Correcting Codec ASIC
Coder/decoder constructed on single integrated-circuit chip. Handles data in variety of formats at rates up to 300 Mbps, correcting up to 3 errors per data block of 256 to 512 bits. Helps reduce cost of transmitting data. Useful in many high-data-rate, bandwidth-limited communication systems such as; personal communication networks, cellular telephone networks, satellite communication systems, high-speed computing networks, broadcasting, and high-reliability data-communication links.
Automated synthesis and verification of configurable DRAM blocks for ASIC's
A highly flexible embedded DRAM compiler is developed which can generate DRAM blocks in the range of 256 bits to 256 Kbits. The compiler is capable of automatically verifying the functionality of the generated DRAM modules. The fully automated verification capability is a key feature that ensures the reliability of the generated blocks. The compiler's architecture, algorithms, verification techniques and the implementation methodology are presented.