Search NASA⌕ Search

SEARCH · Search NASA

Results for “ASIC”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Flexible high speed codec

The project's objective is to develop an advanced high speed coding technology that provides substantial coding gains with limited bandwidth expansion for several common modulation types. The resulting technique is applicable to several continuous and burst communication environments. Decoding provides a significant gain with hard decisions alone and can utilize soft decision information when available from the demodulator to increase the coding gain. The hard decision codec will be implemented using a single application specific integrated circuit (ASIC) chip. It will be capable of coding and decoding as well as some formatting and synchronization functions at data rates up to 300 megabits per second (Mb/s). Code rate is a function of the block length and can vary from 7/8 to 15/16. Length of coded bursts can be any multiple of 32 that is greater than or equal to 256 bits. Coding may be switched in or out on a burst by burst basis with no change in the throughput delay. Reliability information in the form of 3-bit (8-level) soft decisions, can be exploited using applique circuitry around the hard decision codec. This applique circuitry will be discrete logic in the present contract. However, ease of transition to LSI is one of the design guidelines. Discussed here is the selected coding technique. Its application to some communication systems is described. Performance with 4, 8, and 16-ary Phase Shift Keying (PSK) modulation is also presented.

Boyd, R. W.↗
NASA NTRS1991

The MARCOR GPS mobile data system

Market research revealed several key demands for an Automatic Vehicle Location (AVL) Global Positioning System (GPS) radio. The demands were for minimization of urban building blockage, easy programmability to minimize mobile data transmission costs, high accuracy for street map level coordination, interface capability with non-digital Specialized Mobile Radios (SMR), and a selling price close to that of alternatives such as Signposts and Loran-C. A team of experts was assembled to surmount these challenges and deliver a GPS radio for $500 to $1000, which operates at high accuracy in an urban environment and is plug-compatible with nearly all vehicle radios. Among the engineering and production breakthroughs described here are a unique Simultrac (Trademark) approach to satellite tracking, enabling up to eight GPS satellites to be used for position determination with a 2-channel receiver, and a receiver-in-a-microphone design. A powerful Application Specific Integrated Circuit (ASIC) allowed GPS to be brought within easy reach of millions of AVL users such as bus, taxi, and delivery vehicle fleets.

Rothblatt, Martin↗
NASA NTRS1992

Flexible high speed CODEC (FHSC)

This paper describes the on going NASA/Harris FHSC CODEC program. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K ECL logic which can be easily translated to an ECL gate array.

Segallis, G. P.↗
NASA NTRS1993

Fuzzy efficiency optimization of AC induction motors

This paper describes the early states of work to implement a fuzzy logic controller to optimize the efficiency of AC induction motor/adjustable speed drive (ASD) systems running at less than optimal speed and torque conditions. In this paper, the process by which the membership functions of the controller were tuned is discussed and a controller which operates on frequency as well as voltage is proposed. The membership functions for this dual-variable controller are sketched. Additional topics include an approach for fuzzy logic to motor current control which can be used with vector-controlled drives. Incorporation of a fuzzy controller as an application-specific integrated circuit (ASIC) microchip is planned.

Jani, Yashvant↗
NASA NTRS1993

Preliminary results from the MAMA detectors for the SOHO mission

Multi-Anode Microchannel Array (MAMA) detector systems are being fabricated and tested for use in the Solar Ultraviolet Measurements of Emitted Radiation (SUMER) and the Ultraviolet Coronagraph Spectrometer (UVCS) instruments on the ESA/NASA Solar and Heliospheric Observatory (SOHO) mission. The SOHO MAMA detector systems have formats of 360 x 1024 pixels and pixel dimensions of 25 x 25 sq microns and are optimized for operation at Extreme Ultraviolet (EUV) wavelengths between 40 and 160 nm. In this paper we report on the initial results of measurements of the performance characteristics of the first flight-configuration detector system employing the new custom Application Specific Integrated Circuits (ASICs) which are designed to improve both the dynamic range and the uniformity of response. The performance characteristics of this detector system are compared with those of earlier breadboard systems employing discrete-component electronics circuits.

Slater, David C.↗
NASA NTRS1990

Automating analog design: Taming the shrew

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Barlow, A.↗
NASA NTRS1990

Characteristics of a semi-custom library development system

Standard cell and gate array macro libraries are in common use with workstation computer aided design (CAD) tools for application specific integrated circuit (ASIC) semi-custom application and have resulted in significant improvements in the overall design efficiencies as contrasted with custom design methodologies. Similar design methodology enhancements in providing for the efficient development of the library cells is an important factor in responding to the need for continuous technology improvement. The characteristics of a library development system that provides design flexibility and productivity enhancements for the library development engineer as he provides libraries in the state-of-the-art process technologies are presented. An overview of Gould's library development system ('Accolade') is also presented.

Yancey, M.↗
NASA NTRS1990

High performance VLSI telemetry data systems

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

Chesney, J.↗
NASA NTRS1990

Digital control of magnetic bearings in a cryogenic cooler

This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.

Feeley, J.↗
NASA NTRS1993

Wide-bandwidth high-resolution search for extraterrestrial intelligence

A third antenna was added to the system. It is a terrestrial low-gain feed, to act as a veto for local interference. The 3-chip design for a 4 megapoint complex FFT was reduced to finished working hardware. The 4-Megachannel circuit board contains 36 MByte of DRAM, 5 CPLDs, the three large FFT ASICs, and 74 ICs in all. The Austek FDP-based Spectrometer/Power Accumulator (SPA) has now been implemented as a 4-layer printed circuit. A PC interface board has been designed and together with its associated user interface and control software allows an IBM compatible computer to control the SPA board, and facilitates the transfer of spectra to the PC for display, processing, and storage. The Feature Recognizer Array cards receive the stream of modulus words from the 4M FFT cards, and forward a greatly thinned set of reports to the PC's in whose backplane they reside. In particular, a powerful ROM-based state-machine architecture has been adopted, and DRAM has been added to permit integration modes when tracking or reobserving source candidates. The general purpose (GP) array consists of twenty '486 PC class computers, each of which receives and processes the data from a feature extractor/correlator board set. The array performs a first analysis on the provided 'features' and then passes this information on to the workstation. The core workstation software is now written. That is, the communication channels between the user interface, the backend monitor program and the PC's have working software.

Horowitz, Paul↗
NASA NTRS1992

Quartz/fused silica chip carriers

The primary objective of this research and development effort was to develop monolithic microwave integrated circuit (MMIC) packaging which will operate efficiently at millimeter-wave frequencies. The packages incorporated fused silica as the substrate material which was selected due to its favorable electrical properties and potential performance improvement over more conventional materials for Ka-band operation. The first step towards meeting this objective is to develop a package that meets standard mechanical and thermal requirements using fused silica and to be compatible with semiconductor devices operating up to at least 44 GHz. The second step is to modify the package design and add multilayer and multicavity capacity to allow for application specific integrated circuits (ASIC's) to control multiple phase shifters. The final step is to adapt the package design to a phased array module with integral radiating elements. The first task was a continuation of the SBIR Phase 1 work. Phase 1 identified fused silica as a viable substrate material by demonstrating various plating, machining, and adhesion properties. In Phase 2 Task 1, a package was designed and fabricated to validate these findings. Task 2 was to take the next step in packaging and fabricate a multilayer, multichip module (MCM). This package is the predecessor to the phased array module and demonstrates the ability to via fill, circuit print, laminate, and to form vertical interconnects. The final task was to build a phased array module. The radiating elements were to be incorporated into the package instead of connecting to it with wire or ribbon bonds.

Source record↗
NASA NTRS1993

Mongoose: Creation of a Rad-Hard MIPS R3000

This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

Lincoln, Dan↗
NASA NTRS1992

A DRAM compiler algorithm for high performance VLSI embedded memories

In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .

Eldin, A. G.↗
NASA NTRS1993

Telemetry ground system development via the component approach

NASA's deployment of major space projects such as the Earth Observing System (EOS) will demand increased functionality and ground-based telemetry processing performance well above current capabilities. At the NASA/Goddard Space Flight Center, custom hardware and software components have been developed and combined into a unique architecture to address this problem. The hardware components utilize Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to handle data rates up to 300 Mbps. A generalized set of software components, called the Telemetry Processing Control Environment facilitate the rapid construction of control and monitoring functions for the ground-based telemetry processing systems. This combination of hardware and software elements enables rapid construction of flexible, cost-effective telemetry processing systems capable of meeting the performance requirements facing NASA in the coming decade.

Thorn, Karen E.↗
NASA NTRS1993

NASA's spacecraft data system

The NASA Small Explorer Data System (SEDS), a space flight data system developed to support the Small Explorer (SMEX) project, is addressed. The system was flown on the Solar Anomalous Magnetospheric Particle Explorer (SAMPEX) SMEX mission, and with reconfiguration for different requirements will fly on the X-ray Timing Explorer (XTE) and the Tropical Rainfall Measuring Mission (TRMM). SEDS is also foreseen for the Hubble repair mission. Its name was changed to Spacecraft Data System (SDS) in view of expansions. Objectives, SDS hardware, and software are described. Each SDS box contains two computers, data storage memory, uplink (command) reception circuitry, downlink (telemetry) encoding circuitry, Instrument Telemetry Controller (ITC), and spacecraft timing circuitry. The SDS communicates with other subsystems over the MIL-STD-1773 data bus. The SDS software uses a real time Operating System (OS) and the C language. The OS layer, communications and scheduling layer, application task layer, and diagnostic software, are described. Decisions on the use of advanced technologies, such as ASIC's (Application Specific Integrated Circuits) and fiber optics, led to technical improvements, such as lower power and weight, without increasing the risk associated with the data system. The result was a successful SAMPEX development, integration and test, and mission using SEDS, and the upgrading of that system to SDS for TRMM and XTE.

Cudmore, Alan↗
NASA NTRS1994

Synthetic aperture radar signal data compression using block adaptive quantization

This paper describes the design and testing of an on-board SAR signal data compression algorithm for ESA's ENVISAT satellite. The Block Adaptive Quantization (BAQ) algorithm was selected, and optimized for the various operational modes of the ASAR instrument. A flexible BAQ scheme was developed which allows a selection of compression ratio/image quality trade-offs. Test results show the high quality of the SAR images processed from the reconstructed signal data, and the feasibility of on-board implementation using a single ASIC.

Kuduvalli, Gopinath↗
NASA NTRS1994

Hardware description languages

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

Tucker, Jerry H.↗
NASA NTRS1994

A second generation 50 Mbps VLSI level zero processing system prototype

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Harris, Jonathan C.↗