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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Topics include an overview of On-board science data processing, software upset mitigation, on-board data reduction, on-board products, HyspIRI demonstration testbed, SpaceCube 2.0 block diagram, and processor comparison.
The year 2008 was an historic one for both our country and the Space Studies Board (SSB). The United States elected a new president. His first task has been to cope with an economic crisis of historic proportions. In the same year, the United States celebrated the 50th anniversary of its first spaceflight, and the SSB celebrated its 50th anniversary. As we in the space community looked back, we also looked forward. The year 2008 was truly a year of transition, for the country and for the space enterprise. Under Lennard Fisk's continued leadership, the SSB completed its year-long seminar series, Forging the Future of Space Science, which highlighted the accomplishments of space science over the past 50 years and looked ahead to the next 50 years of discoveries that await us. During the first half of the year, events were held in Tallahasse, Florida; Austin, Texas; Paris, France (in conjunction with the Committee on Space Research, which is headquartered here); Boulder, Colorado; and Fairmont, West Virginia. The series culminated in a celebration at the National Air and Space Museum in Washington, D.C., on June 26, .50 years to the day after the SSB was created. At that event, the Board presented its first James A. Van Allen Lectureship to Frank McDonald. The recent economic crisis has made it obvious that the U.S. economy does not stand alone. The global economy is becoming more and more integrated. The space enterprise cannot avoid this trend. In November, the SSB conducted a workshop in conjunction with the Aeronautics and Space Engineering Board entitled 'Future International Space Cooperation and Competition in a Globalizing World'. Its goals were to assess the current state of international cooperation and competition in space and to discuss ways in which new and emerging space powers might be better integrated into the global space community.
An increasing number of parts are designed with digital control interfaces, including phase shifters and variable attenuators. When designing an antenna array in which each antenna has independent amplitude and phase control, the number of digital control lines that must be set simultaneously can grow very large. Use of a parallel interface would require separate line drivers, more parts, and thus additional failure points. A convenient form of control where single-phase shifters or attenuators could be set or the whole set could be programmed with an update rate of 100 Hz is needed to solve this problem. A digital interface board with a field-programmable gate array (FPGA) can simultaneously control an essentially arbitrary number of digital control lines with a serial command interface requiring only three wires. A small set of short, high-level commands provides a simple programming interface for an external controller. Parity bits are used to validate the control commands. Output timing is controlled within the FPGA to allow for rapid update rates of the phase shifters and attenuators. This technology has been used to set and monitor eight 5-bit control signals via a serial UART (universal asynchronous receiver/transmitter) interface. The digital interface board controls the phase and amplitude of the signals for each element in the array. A host computer running Agilent VEE sends commands via serial UART connection to a Xilinx VirtexII FPGA. The commands are decoded, and either outputs are set or telemetry data is sent back to the host computer describing the status and the current phase and amplitude settings. This technology is an integral part of a closed-loop system in which the angle of arrival of an X-band uplink signal is detected and the appropriate phase shifts are applied to the Ka-band downlink signal to electronically steer the array back in the direction of the uplink signal. It will also be used in the non-beam-steering case to compensate for phase shift variations through power amplifiers. The digital interface board can be used to set four 5-bit phase shifters and four 5-bit attenuators and monitor their current settings. Additionally, it is useful outside of the closed-loop system for beamsteering alone. When the VEE program is started, it prompts the user to initialize variables (to zero) or skip initialization. After that, the program enters into a continuous loop waiting for the telemetry period to elapse or a button to be pushed. A telemetry request is sent when the telemetry period is elapsed (every five seconds). Pushing one of the set or reset buttons will send the appropriate command. When a command is sent, the interface status is returned, and the user will be notified by a pop-up window if any error has occurred. The program runs until the End Program button is depressed.
Spacesuit navigation is one component of NASA s efforts to return humans to the Moon. Studies performed at the NASA Glenn Research Center (GRC) considered various navigation technologies and filtering approaches to enable navigation on the lunar surface. As part of this effort, microelectromechanical systems (MEMS) inertial measurement units (IMUs) were studied to determine if they could supplement a radiometric infrastructure. MEMS IMUs were included in the Lunar Extra-Vehicular Activity Crewmember Location Determination System (LECLDS) testbed during NASA s annual Desert Research and Technology Studies (D-RATS) event in 2009 and 2010. The testbed included one IMU in 2009 and three IMUs in 2010, along with a custom circuit board interfacing between the navigation processor and each IMU. The board was revised for the 2010 test, and this paper documents the design details of this latest revision of the interface circuit board and firmware.
This is a board-level design document for Modular Integrated Stackable Layers (MISL) MI_MSP430A board (PIN MSP430F5438A). The Board Design Document (BDD) contains the description, features of microcontroller, electrical and mechanical design, and drawings.
This paper will explore the ability of printed circuit boards laminated with a Carbon Core Laminate to transfer heat vs. standard printed circuit boards that use only thick layers of copper. The paper will compare the differences in heat transfer performance of printed circuit boards with and without CCL.
This paper describes the motivation for the creation of the Vulnerability, Impacts, Adaptation and Climate Services (VIACS) Advisory Board for the Sixth Phase of the Coupled Model Intercomparison Project (CMIP6), its initial activities, and its plans to serve as a bridge between climate change applications experts and climate modelers. The climate change application community comprises researchers and other specialists who use climate information (alongside socioeconomic and other environmental information) to analyze vulnerability, impacts, and adaptation of natural systems and society in relation to past, ongoing, and projected future climate change. Much of this activity is directed toward the co-development of information needed by decisionmakers for managing projected risks. CMIP6 provides a unique opportunity to facilitate a two-way dialog between climate modelers and VIACS experts who are looking to apply CMIP6 results for a wide array of research and climate services objectives. The VIACS Advisory Board convenes leaders of major impact sectors, international programs, and climate services to solicit community feedback that increases the applications relevance of the CMIP6-Endorsed Model Intercomparison Projects (MIPs). As an illustration of its potential, the VIACS community provided CMIP6 leadership with a list of prioritized climate model variables and MIP experiments of the greatest interest to the climate model applications community, indicating the applicability and societal relevance of climate model simulation outputs. The VIACS Advisory Board also recommended an impacts version of Obs4MIPs (observational datasets) and indicated user needs for the gridding and processing of model output.
A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm.times.7 cm.
As more organizations transition from traditional document-centric systems engineering to a model-based approach, many are challenged to train their staff in new languages, tools, and methodologies, while managing the expectations of stakeholders and their expected model outcomes. In particular, challenges associated with learning a new modeling language and developing skills in the 'art' of modeling present organizations with formidable obstacles to realizing this transition. This paper hypothesizes that systems engineers may more readily learn how to correctly model with SysML, and develop intuition about the art of modeling and using patterns, if their learning references a commonly and thoroughly-understood subject, such as a board game. This paper presents a case for the use of board games as subject matter for new modelers. It demonstrates the concept with a sample model of Hasbro's popular board game, Monopoly, and discusses the limitations of this approach and potential adaptations that may broaden the applicability of the learned skills to projects. Finally, results from a small feasibility assessment and concepts for more formal study to evaluate the hypothesis are presented.
As more organizations transition from traditional document-centric systems engineering to a model-based approach, many are challenged to train their staff in new languages, tools, and methodologies, and manage the expectations of stakeholders and their expected model outcomes. In particular, challenges associated with learning a new modeling language and developing skills in the 'art' of modeling present organizations with formidable obstacles to realizing this transition. This paper hypothesizes that systems engineers may more readily learn how to correctly model with SysML, and develop intuition about the art of modeling and using patterns, if their learning references a commonly and thoroughly-understood subject matter, such as a board game. This paper presents a case for the use of board games as subject matter for new modelers, demonstrates the concept with a sample model of Hasbro's popular board game, Monopoly, and discusses the limitations of this approach and potential adaptations that may broaden the applicability of the learned skills to projects.
This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.
This paper reviews the evolution and emerging direction of superconducting electric machines that employ onboard cryocoolers integrated directly into the rotor, eliminating the need for cryogenic fluid coupling and, in some cases, rotary seals. Traditional low-temperature superconducting (LTS) machines relied on external cryogenic systems and liquid helium transfer couplers, which introduced excessive complexity, poor reliability, and significant parasitic energy losses. The advent of high-temperature superconductors (HTS) has enabled compact, closed-cycle cryocoolers that support self-contained, fluid-free refrigeration architectures suitable for rotating applications. This paper examines the key technological challenges associated with on-board cryocooler integration and reviews three representative efforts by KAIST, NASA, and Hinetics, each illustrating distinct strategies and milestones toward practical implementation. KAIST demonstrated early proof-of-concept for rotating machines with on-board cryocoolers, NASA developed a shaft-integrated Stirling-type pulse tube cryocooler for a 1.4 MW hybrid-electric motor, and Hinetics achieved full-scale validation of a self-contained HTS rotor incorporating a commercial Stirling cryocooler and spoke-suspension torque tube. Collectively, these achievements confirm the technical feasibility of on-board cryogenic refrigeration and highlight steady progress toward compact and efficient superconducting rotating systems across various applications. Embedding cryocoolers directly within the rotor enables practical, efficient, and commercially viable superconducting propulsion technologies.
Multilayer board compared to two-sided board circuits, discussing circuit reliability, flexibility, cost, packaging density, etc
Volume II of the Report contains appendices that were cited in Volume I. The Columbia Accident Investigation Board produced many of these appendices as working papers during the investigation into the February 1, 2003 destruction of the Space Shuttle Columbia. Other appendices were produced by other organizations (mainly NASA) in support of the Board investigation. In the case of documents that have been published by others, they are included here in the interest of establishing a complete record, but often at less than full page size. Contents include: CAIB Technical Documents Cited in the Report: Reader's Guide to Volume II; Appendix D. a Supplement to the Report; Appendix D.b Corrections to Volume I of the Report; Appendix D.1 STS-107 Training Investigation; Appendix D.2 Payload Operations Checklist 3; Appendix D.3 Fault Tree Closure Summary; Appendix D.4 Fault Tree Elements - Not Closed; Appendix D.5 Space Weather Conditions; Appendix D.6 Payload and Payload Integration; Appendix D.7 Working Scenario; Appendix D.8 Debris Transport Analysis; Appendix D.9 Data Review and Timeline Reconstruction Report; Appendix D.10 Debris Recovery; Appendix D.11 STS-107 Columbia Reconstruction Report; Appendix D.12 Impact Modeling; Appendix D.13 STS-107 In-Flight Options Assessment; Appendix D.14 Orbiter Major Modification (OMM) Review; Appendix D.15 Maintenance, Material, and Management Inputs; Appendix D.16 Public Safety Analysis; Appendix D.17 MER Manager's Tiger Team Checklist; Appendix D.18 Past Reports Review; Appendix D.19 Qualification and Interpretation of Sensor Data from STS-107; Appendix D.20 Bolt Catcher Debris Analysis.
In the course of its inquiry into the February 1, 2003 destruction of the Space Shuttle Columbia, the Columbia Accident Investigation Board conducted a series of public hearings at Houston, Texas; Cape Canaveral, Florida; and Washington, DC. Testimony from these hearings was recorded and then transcribed. This appendix, Volume VI of the Report, is a compilation of those transcripts. Contents: Transcripts of Board Public Hearings; Appendix H.1 March 6, 2003 Houston, Texas; Appendix H.2 March 17, 2003 Houston, Texas; Appendix H.3 March 18, 2003 Houston, Texas; Appendix H. 4 March 25, 2003 Cape Canaveral, Florida; Appendix H.5 March 26, 2003 Cape Canaveral, Florida; Appendix H.6 April 7, 2003 Houston, Texas; Appendix H.7 April 8, 2003 Houston, Texas; Appendix H.8 April 23, 2003 Houston, Texas; Appendix H.9 May 6, 2003 Houston, Texas; Appendix H.10 June 12, 2003 Washington, DC.
This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications on custom hardware, and consideration on implementation approaches. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.
Use of Doppler velocity measurement in spaceborne precipitation radar is highly desirable, since it can allow more accurate retrieval of atmospheric latent heating, which depends on both cloud and rain microphysical processes and on dynamical processes, namely, vertical updrafts and downdrafts. However, if the rain within the antenna beam is very non-uniform, biases can result with conventional pulse-pair processing, and more sophisticated processing is required. The solution is a time-frequency approach, which uses the full Doppler spectrum at each point in time. Since precipitation radars normally operate continuously and collect large amounts of data, real-time, on-board processing of data is needed to reduce the data rate. The objective of this work is to develop an on-board data processor for spaceborne Doppler precipitation radar, using field-programmable gate array (FPGA) technology. This paper describes the simulations and analysis that have been completed during the first year of the project. This includes both analytical calculations and bit-true simulations that allow the effects of finite word length to be explored. Tradeoffs have also been considered between speed and space within the chosen FPGA part. The results of these analyses have been used to develop a complete set of requirements for the processor. Initial design work has begun, based on these requirements. The design is being implemented in Verilog, and a description of this early design effort is also be given.
The Earth Sciences Decadal Survey identifies a multiangle, multispectral, high-accuracy polarization imager as one requirement for the Aerosol-Cloud-Ecosystem (ACE) mission. JPL has been developing a Multiangle SpectroPolarimetric Imager (MSPI) as a candidate to fill this need. A key technology development needed for MSPI is on-board signal processing to calculate polarimetry data as imaged by each of the 9 cameras forming the instrument. With funding from NASA's Advanced Information Systems Technology (AIST) Program, JPL is solving the real-time data processing requirements to demonstrate, for the first time, how signal data at 95 Mbytes/sec over 16-channels for each of the 9 multiangle cameras in the spaceborne instrument can be reduced on-board to 0.45 Mbytes/sec. This will produce the intensity and polarization data needed to characterize aerosol and cloud microphysical properties. Using the Xilinx Virtex-5 FPGA including PowerPC440 processors we have implemented a least squares fitting algorithm that extracts intensity and polarimetric parameters in real-time, thereby substantially reducing the image data volume for spacecraft downlink without loss of science information.