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DOE OSTI2026

Plasma flow generation and particle acceleration from expanding magnetic bubbles

Impulsive plasma dynamics in the laboratory are often driven by rising electric currents, yet their quantitative plasma response has not been well established. By means of fully kinetic particle-in-cell simulations and laser-driven capacitor-coil experiments, we show that a rising current expels plasma, forming an expanding magnetic bubble and accelerating particles. The expansion front velocity scales with the Alfvén speed determined by the magnetic field at its inner edge and the plasma density at its outer edge. This mechanism establishes impulsive current drive as a fundamental way that generates plasma flows and accelerates particles in laboratory plasmas, with potential relevance to astrophysics.

Zhang, Yang [Princeton University, NJ (United Stat↗

DOE OSTI2026

Endogenous Interface Pricing for Consistent Transmission–Distribution Co-Optimization With Discrete Distribution Controls

This paper proposes an endogenous interface pricing model for day-ahead transmission–distribution co-optimization that co-determines the interface locational marginal price (LMP) and the transmission–distribution exchange, ensuring price–dispatch consistency while optimally scheduling discrete distribution controls. The formulation couples a DC optimal power flow (OPF) with a branch-flow AC OPF that schedules distributed energy resources (DERs), tap-changer settings, capacitor banks (CBs), and multi-period energy storage systems (ESSs) under feeder voltage and current limits, and is solved as a mixed-integer second-order cone program (MISOCP). In a T14–D33 system, coordinated device scheduling recovers about 90% of the distribution-to-transmission export achievable in a reference case that ignores distribution network (DN) limits, while satisfying a 1.05 p.u. voltage upper bound. In a T39–D34/D37/D123 system, a sequential decoupled benchmark produces interface LMP distortions up to 12.5% and a 7.28% mismatch in net export energy, whereas the proposed model removes these distortions and the associated settlement mismatches. Second-order cone (SOC) relaxation gaps remain below $10^{-3}$ in all cases.

Noh, Seung-Gil↗

DOE OSTI2024

Direct Power Control of Back to Back Modular Multilevel Converter with Advanced Grid Support Functions for Grid Forming Application

Possibility of using back-to-back modular multilevel converter system with a direct power control architecture has been investigated in this paper. The rectifier side is controlled to be in grid following mode whereas the inverter side is controlled in grid forming mode. Both the sides’ local controllers use Lyapunov energy function based architecture to accomplish the objective of active and reactive power control as well as maintaining a fixed user defined voltage over the dc bus on the rectifier side. Therefore, the proposed direct power control architecture has embedded dc bus control architecture to maintain fixed user defined value of the capacitors. Similar architecture is implemented on the inverter side to accomplish either voltage control during grid forming or power control during grid following. Advanced grid support functionalities based on IEEE-1547-2018 is implemented and utilized to generate the reference values for either the rectifier or the inverter sides. The overall system is modeled based on MATLAB/Simulink and PLECS domain and various important case studies to verify the efficacy of the overall system has been presented.

direct power control (DPC)↗

DOE OSTI2024

Stacked-Die SiC Half-Bridge Module with Minimum Loop Inductance

Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.

Ribeiro, Pedro↗

DOE OSTI2025

A Cost-Effective Wave Energy Harvesting System with Maximum Power Point Tracking Capability

In this paper, we propose a low-cost bidirectional four-switch inverter that transfers three-phase energy between a permanent magnet synchronous generator (PMSG) driven by a wave energy collector and the power grid or a local ac load. To achieve high control performance, the machine-side inverter uses a high-gain observer for rotor position estimation and a Lyapunov-based approach for torque control. For the gridside inverter control, we estimate the filter capacitor voltage with a model reference adaptive system and control the dc-link voltage with a Lyapunov-based energy function. We also track the maximum power point from the sea waves with an integral control law that actively matches the generator impedance with that of the wave collection device. The proposed system supports both grid-following/forming modes. We validate our control design with simulation results on a 3-kW hardware setup.

wave energy, power systems integration, control de↗

DOE OSTI2024

Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET

Here, in this work, we present a variation-tolerant and energy-efficient charge-domain Ferroelectric FET (FeFET) based Compute-in-Memory (CiM) array design that is compatible with both binary and multi-level cell memory sensing. We demonstrate that: 1) by exploiting FeFET as a nonvolatile switch, its high ON/OFF ratio in the subthreshold region can suppress the error introduced by the inaccurate ON state conductance, thus realizing robust CiM operations, unlike the current-domain CiM design where the computation results is highly sensitive to the device conductance variation; 2) by leveraging a dense dynamic random access memory (DRAM)-like 1FeFET1C cell structure, the proposed design benefits from the existing high density DRAM establishment while also significantly relaxing the capacitor retention and transistor leakage requirement; 3) the charge-domain CiM supports both binary FeFET with minimum overhead and MLC FeFET with tolerable latency for MLC state sensing, whose efficacy is validated experimentally on both cell-level and array-level; 4) the proposed CiM shows much better device variation resilience than conventional current-domain CiM, and also improves inference accuracy. Macro-level evaluation results demonstrate significantly higher energy efficiency and area efficiency compared to prior CiM works.

Duan, Jiahui [University of Notre Dame, IN (United↗

DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗

DOE OSTI2025

The Upgrade of the SNS Extraction Kicker Power Supplies for the Proton Power Upgrade

The Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS) aims to enhance the linear accelerator's power output from 1.4 to 2.8 megawatts. A critical focus lies on upgrading the Extraction Kicker Power Supplies to handle the amplified beam power. The existing capacitor charging power supplies lacked the capability to charge the Blumlein-type Pulse Forming Network (PFN) to the required 40 kV at a repetition rate of 60 Hz. To address this limitation, an initial solution involving the use of a resonant charging circuit was proposed. However, a challenge arose with a self-firing issue in the thyristor switch, which proved unsolvable within the given timeframe. Facing a critical decision point in the project, an alternative approach was explored: integrating a supplementary power supply to enhance the overall power capacity. This solution was tested and ultimately chosen as the path forward. To accommodate the additional power supply, the power distribution system had to undergo upgrades. Throughout this endeavor, a comprehensive examination of the system took place, with meticulous identification of key components. This paper delves into the technical challenges encountered during the process and the corresponding solutions that were implemented.

Tan, Yugang [ORNL] (ORCID:0000000155968252)↗

DOE OSTI2025

Inverse Segmented Motor Drive Using Dual ANPC Inverters for Common-Mode Voltage and Neutral-Point Current Cancellation

This article proposes an inverse segmented motor drive (SgMD) utilizing dual active neutral point clamped (ANPC) inverters. In the proposed configuration, the neutral point current and common-mode (CM) voltage is topologically canceled, achieving zero total neutral point current and CM voltage under ideal conditions. Also, the zero total neutral point current minimizes the neutral point voltage imbalance in ANPC inverters. The mechanisms behind neutral point current and CM voltage cancellation in the proposed inverse SgMD are first introduced. The modifications to the motor windings for implementing the inverse SgMD are explained, showing that a standard motor can be readily adapted for the proposed configuration. A space vector modulation (SVM) scheme tailored for the proposed topology is presented, along with a carrier-based implementation. Simulation results validate that the proposed topology can achieve zero total CM voltage and neutral point current. It is also shown that the proposed inverse SgMD can reduce neutral point voltage fluctuation by about 90% and RMS current stress in the dc-link capacitors by about 43% compared to the conventional SgMD.

Lee, Sangwhee [ORNL] (ORCID:0000000335490057)↗

DOE OSTI2024

Data-Driven Digital Twin for Reliability Assessment of DC/DC Buck Converter

In commercial applications, the operation of DC/DC converters significantly impacts overall system performance and long-term reliability. This study introduces a data-driven digital twin (DT) approach for estimating critical degradation parameters of DC/DC BUCK converter under steady-state condition. Initially, a circuit-level MATLAB/Simulink digital model (DM C ) is refined against a hardware prototype’s switching model dataset using offline particle swarm optimization. The optimized digital model’s steady-state response is then verified with its average model response while varying the duty and load. Subsequently, degradation profiles are imposed on the inductor, capacitor, MOSFET in the DMC. A large dataset is generated from this model, allowing training, validation, and testing of machine learning (ML) models for component health regression tasks. The proposed method employs random forest ML models, achieving impressive regression results with a squared R value as high as 0.99978 and a root mean square error of 4.2× 10 –6 . The method is further validated on a medium power level DC/DC BUCK prototype with varying load conditions, and includes the analysis of MOSFET’s on-resistance under degradation conditions. This data-driven DT method shows promise for identifying parasitic degradation and ohmic loss parameters, enhancing converter reliability assessments in a non-invasive, generalized, and computationally efficient manner.

14 SOLAR ENERGY↗

DOE OSTI2026

MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator

We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.

36 MATERIALS SCIENCE↗

DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗

DOE OSTI2024

Experimental Analysis of Distribution Network Voltage Regulation Using Smart Inverters

Smart inverters (SIs) have demonstrated their potential to provide grid services for both transmission and distribution systems. One of these grid services, distribution network voltage regulation by SIs, has the potential to improve network voltage regulation through controlling the reactive and active power output of the SIs. Voltage regulation by SIs will be distributed and might be better suited to controlling local conditions to complement traditional voltage-regulating assets, e.g., tap-changing transformers, capacitor banks, and line voltage regulators. There is a gap in the literature on comparing the SI response characteristics when the SIs are controlled by a local controller or external control signals. This paper presents an experimental study to characterize SI reactive power regulation responses to two different control methods: autonomous control and remote dispatch. We found that SI reactive power regulation responses exhibit important differences between these methods in terms of delays and ramp rate. Finally, power-hardware-in-the-loop (PHIL) tests were conducted to evaluate the performance of these two methods. The PHIL test results show that the SI response characteristics for autonomous control and remote dispatch need to be considered when planning for distribution network voltage regulation using SIs.

autonomous control↗

DOE OSTI2024

Development of an MKID frequency-to-pixel LED mapper for SPT-3G+

SPT-3G+ is the next-generation camera for the South Pole Telescope (SPT). SPT is designed to measure the cosmic microwave background (CMB) and the mm/sub-mm sky. The planned focal plane consists of 34,000 microwave kinetic inductance detectors (MKIDs), divided among three observing bands centered at 220, 285, and 345 GHz. Each readout line is designed to measure 800 MKIDs over a 500 MHz bandwidth, which places stringent constraints on the accuracy of the frequency placement required to limit resonator collisions that reduce the overall detector yield. To meet this constraint, we are developing a two-step process that first optically maps the resonance to a physical pixel location, and then next trims the interdigitated capacitor (IDC) to adjust the resonator frequency. We present a cryogenic LED apparatus operable at 300 mK for the optical illumination of SPT-3G+ detector arrays. We demonstrate integration of the LED controls with the GHz readout electronics (RF-ICE) to take data on an array of prototype SPT-3G+ detectors. We show that this technique is useful for characterizing defects in the resonator frequency across the detector array and will allow for improvements in the detector yield.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2024

Simulation-Based Analysis of Feeder Operation with Different PV Smart Inverter Functions on an Actual Distribution System: Preprint

High penetration of photovoltaics (PV) in distribution feeders can cause problems, such as overvoltage, reverse power flow, and large net load changes. Traditional voltage regulation devices, such as capacitors and voltage regulators, can solve some of these problems but might have some delays. Today, smart inverters are gradually being used to provide voltage regulation and frequency support in distribution systems. Different smart inverter settings have been recommended in various rules and standards; however, the potential benefits and their impacts on distribution system operation are not well compared and studied. This paper presents a comparison of different smart inverter settings as applied to a distribution system. An actual feeder model from San Diego Gas & Electric Company is used to conduct the simulation. Additionally, a load disaggregation method is proposed to disaggregate the load and PV profile for each load location using advanced metering infrastructure net load measurements. Then, different smart inverter settings are applied to the PV systems in the feeder, and the simulation results are compared. The results show that the implementation of specific functions of smart inverters can reduce voltage exceedances, and the utility can determine the specific inverter setting based on its operational requirements.

distribution system↗

DOE OSTI2026

Generalized Theory and Realization of Reconfigurable Bandpass Filtering Equalizers

Here, in this article, a generalized theory of bandpass filtering equalizers is proposed. A filtering equalizer is a device that combines the frequency-selective properties of a filter with the controllable slope of an equalizer into a single component. The equations used to design the function for a desired slope are provided, and the design methodology to determine the necessary filtering polynomials is also shown. The controllable slope of the dual-function component is realized using variable capacitors, which are used to tune both a transmission zero and a matching network to achieve the desired slope. A third-order bandpass filtering equalizer is designed, fabricated, and measured to verify the generalized theory. The component is designed to operate at 1 GHz with a slope that can be reconfigured from 1 to 3 dB along the passband. This proposed filtering equalizer demonstrates the feasibility of a tunable, low-cost, size, weight, and power (C-SWaP) solution to enable increased flatness in the overall system response and thereby decrease the error vector magnitude (EVM) of future radio frequency (RF) systems and a design process that allows for future development of filtering equalizers.

Filter↗

DOE OSTI2024

Output Capacitance Loss of GaN HEMTs in Steady-State Switching

The output capacitance (C OSS ) loss, a loss produced when the device’s output capacitor is charged and discharged, has become a concern for GaN high electron mobility transistors (HEMTs) in high-frequency applications. This work presents a new, easy-to-implement method for the C OSS loss characterization based on the unclamped inductive switching (UIS) setup. As compared to prior approaches, this method involves the device’s ON-state conduction and could measure the C OSS loss in a single pulse and the steady-state switching. The C OSS loss of three types of mainstream commercial GaN HEMTs is characterized, which exhibit some common dependencies including a non-monotonic relation with the dv/dt (or resonance frequency), a linear relation with the ON-state current, a power-law relation with the peak blocking voltage, and little temperature dependence. In addition, their C OSS losses all show minimal distinctions in a single pulse and the steady-state switching, despite the increased on-resistance in the steady-state switching. Furthermore, this suggests that the traps accounting for the C OSS loss possess different de-trapping time constants as compared to the traps governing the dynamic on-resistance. Finally, a unified model is established to describe the C OSS loss of all three types of GaN HEMTs. These results provide important references for the high-frequency application of GaN HEMTs and new insights into the physical origin of their C OSS loss.1

42 ENGINEERING↗

DOE OSTI2024

A Compact, Single Stage, >1 kV Medium-Voltage Line Impedance Stabilization Network

This paper presents the design of a single-phase, single-stage line impedance stabilization network (LISN) for medium-voltage (MV) applications. More than 1 kV rated widebandgap (WBG) power semiconductor switches are increasingly utilized in new, emerging power electronics energy systems to improve power density and efficiency. However, due to inherently fast-switching speeds, WBG switch modules emit considerable electromagnetic interference (EMI) (e.g., common mode (CM) or differential mode (DM)). State-of-the-art offers standardized LISN solutions to validate and certify the new energy system for electromagnetic compatibility (EMC). However, most are for low voltage applications (i.e., < 1 kV). MV LISNs (i.e., > 1 kV) are rare until recently and literature does not provide sufficient guidelines for designing and characterizing such devices. It has been a critical challenge for many scientists and engineers to reliably certify the emerging MV energy systems (e.g., electric ships and aircraft). This paper addresses such a technology gap. Specifically, a CISPR 16-1-2 compliant 50Ω/50μH LISN with 1.5kV, 75A and 30MHz measurement capability has been proposed. Detailed performance study versus non-linear parasitic parameters variations in MV inductors and capacitors have been done. Based on new understandings, novel techniques to intuitively mitigate unwanted parasitic have been proposed to develop the proposed LISN successfully. Thorough characterization of important LISN parameters are presented and factors influencing them are analyzed. A rigorous analysis, experimental tests, and in-depth comparisons over state-of-the-art have been made to validate the effectiveness. This is done through the state-of-the-art 300kVA MV EMI testbed.

42 ENGINEERING↗