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At least 127 records · Page 7

All sources NASA NTRS DOE OSTI

NASA NTRS1993

Another Nulling Hall-Effect Current-Measuring Circuit

Lightweight, low-power circuit provides noncontact measurement of alternating or direct current of many ampheres in main conductor. Advantages of circuit over other nulling Hall-effect current-measuring circuits is stability and accuracy increased by putting both analog-to-digital and digital-to-analog converters in nulling feedback loop. Converters and rest of circuit designed for operation at sampling rate of 100 kHz, but rate changed to alter time or frequency response of circuit.

Thibodeau, Phillip E.↗

NASA NTRS1992

Circuit design tool. User's manual, revision 2

The CAM chip design was produced in a UNIX software environment using a design tool that supports definition of digital electronic modules, composition of these modules into higher level circuits, and event-driven simulation of these circuits. Our design tool provides an interface whose goals include straightforward but flexible primitive module definition and circuit composition, efficient simulation, and a debugging environment that facilitates design verification and alteration. The tool provides a set of primitive modules which can be composed into higher level circuits. Each module is a C-language subroutine that uses a set of interface protocols understood by the design tool. Primitives can be altered simply by recoding their C-code image; in addition new primitives can be added allowing higher level circuits to be described in C-code rather than as a composition of primitive modules--this feature can greatly enhance the speed of simulation.

Miyake, Keith M.↗

NASA NTRS1991

Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure.

Leonard, Regis F.↗

NASA NTRS1990

Self arbitrated VLSI asynchronous sequential circuits

A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

Whitaker, S.↗

NASA NTRS1990

Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits

The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.

Buehler, M.↗

NASA NTRS1991

High accuracy switched-current circuits using an improved dynamic mirror

The switched-current technique, a recently developed circuit approach to analog signal processing, has emerged as an alternative/compliment to the well established switched-capacitor circuit technique. High speed switched-current circuits offer potential cost and power savings over slower switched-capacitor circuits. Accuracy improvements are a primary concern at this stage in the development of the switched-current technique. Use of the dynamic current mirror has produced circuits that are insensitive to transistor matching errors. The dynamic current mirror has been limited by other sources of error including clock-feedthrough and voltage transient errors. In this paper we present an improved switched-current building block using the dynamic current mirror. Utilizing current feedback the errors due to current imbalance in the dynamic current mirror are reduced. Simulations indicate that this feedback can reduce total harmonic distortion by as much as 9 dB. Additionally, we have developed a clock-feedthrough reduction scheme for which simulations reveal a potential 10 dB total harmonic distortion improvement. The clock-feedthrough reduction scheme also significantly reduces offset errors and allows for cancellation with a constant current source. Experimental results confirm the simulated improvements.

Zweigle, G.↗

NASA NTRS1991

Pulse mode VLSI asynchronous circuits

A new basic VLSI circuit element is presented that can be used to realize pulse mode asynchronous sequential circuits. A synthesis procedure is developed along with an unconventional state assignment procedure. Level input asynchronous sequential circuits can be realized by converting a regular flow table into a differential mode flow table, thereby allowing the new synthesis technique to be general. The new circuits tolerate 1-1 crossovers. This circuit also provides a means for state sequence detection and real time fault detection.

Chen, Q.↗

NASA NTRS1993

Testing self-timed circuits using scan paths

Testing is an essential part of any digital system design and one that can be made much easier if testing is considered during the design process rather than after the system is complete. There are a number of techniques for integrating testability into system design, but many of these traditional testing methods used for synchronous circuits are not directly applicable to non-clocked asynchronous circuits. As a result, many asynchronous circuits do not employ design for testability techniques. A method of using the familiar model of scan paths modified to test self-timed systems are presented. Specifically, circuits designed using a library of self-timed modules to assemble systems with two-phase transition control and bundled data paths are considered. The method involves modifying these self-timed modules such that circuits designed from them have a built-in scan path.

Khoche, Ajay↗

NASA NTRS1993

Robust neural classifier circuits using asynchronous design

Aerospace neural circuits must be adaptive, offer a practical size-performance ratio, and be environmentally robust. Our approach to building such circuits combines asynchronous design with a new fuzzy/neural classifier model. Asynchronous circuits offer many design advantages for neural hardware and our hybrid fuzzy/neural model, using mainly min and max operators, promises a low circuit complexity. The general approach is described and a description of a use of rule-induction to further reduce circuit complexity is described.

Hurdle, John F.↗

NASA NTRS1993

Design and implementation of GaAs HBT circuits with ACME

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Hutchings, Brad L.↗

NASA NTRS1994

Document analysis with neural net circuits

Document analysis is one of the main applications of machine vision today and offers great opportunities for neural net circuits. Despite more and more data processing with computers, the number of paper documents is still increasing rapidly. A fast translation of data from paper into electronic format is needed almost everywhere, and when done manually, this is a time consuming process. Markets range from small scanners for personal use to high-volume document analysis systems, such as address readers for the postal service or check processing systems for banks. A major concern with present systems is the accuracy of the automatic interpretation. Today's algorithms fail miserably when noise is present, when print quality is poor, or when the layout is complex. A common approach to circumvent these problems is to restrict the variations of the documents handled by a system. In our laboratory, we had the best luck with circuits implementing basic functions, such as convolutions, that can be used in many different algorithms. To illustrate the flexibility of this approach, three applications of the NET32K circuit are described in this short viewgraph presentation: locating address blocks, cleaning document images by removing noise, and locating areas of interest in personal checks to improve image compression. Several of the ideas realized in this circuit that were inspired by neural nets, such as analog computation with a low resolution, resulted in a chip that is well suited for real-world document analysis applications and that compares favorably with alternative, 'conventional' circuits.

Graf, Hans Peter↗

NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

Lohn, Jason D.↗

NASA NTRS2001

Battery Cell By-Pass Circuit

The invention is a circuit and method of limiting the charging current voltage from a power supply net work applied to an individual cell of a plurality of cells making up a battery being charged in series. It is particularly designed for use with batteries that can be damaged by overcharging, such as Lithium-ion type batteries. In detail. the method includes the following steps: 1) sensing the actual voltage level of the individual cell; 2) comparing the actual voltage level of the individual cell with a reference value and providing an error signal representative thereof; and 3) by-passing the charging current around individual cell necessary to keep the individual cell voltage level generally equal a specific voltage level while continuing to charge the remaining cells. Preferably this is accomplished by by-passing the charging current around the individual cell if said actual voltage level is above the specific voltage level and allowing the charging current to the individual cell if the actual voltage level is equal or less than the specific voltage level. In the step of bypassing the charging current, the by-passed current is transferred at a proper voltage level to the power supply. The by-pass circuit a voltage comparison circuit is used to compare the actual voltage level of the individual cell with a reference value and to provide an error signal representative thereof. A third circuit, designed to be responsive to the error signal, is provided for maintaining the individual cell voltage level generally equal to the specific voltage level. Circuitry is provided in the third circuit for bypassing charging current around the individual cell if the actual voltage level is above the specific voltage level and transfers the excess charging current to the power supply net work. The circuitry also allows charging of the individual cell if the actual voltage level is equal or less than the specific voltage level.

Evers, Jeffrey↗

NASA NTRS2001

Battery Cell By-Pass Circuit

Susan J Mumaw↗

NASA NTRS2002

34% Efficient InGaP/GaAs/GaSb Cell-Interconnected-Circuits for Line-Focus Concentrator Arrays

While monolithic multi-junction cells are preferred for flat plate arrays, mechanically stacked multi-junction cells are superior for solar concentrator applications. Reasons for this are that the mechanical stacked configuration with high efficiency Gallium Antimonide cells allows utilization of a much wider range of the solar energy spectrum, and the ability to use voltage matched interconnects results in full use of low bandgap cell currents. Herein, data are presented for simple two terminal voltage-matched circuits using InGaP/GaAs/GaSb stacked cells showing 34% average circuit efficiency for a lot of 12 circuits given prismatic covers. These circuits have been designed to fit into the ultralight Stretched Lens Array being developed by NASA. With these new cell-interconnected-circuits, we project that the power density at GEO operating temperature can be increased from 296 W/m2 to 350 W/m2 while maintaining the specific power at 190 W/kg at the full wing level.

Fraas, L. M.↗

NASA NTRS1999

Finite Ground Coplanar (FGC) Waveguide: Characteristics and Advantages Evaluated for Radiofrequency and Wireless Communication Circuits

Researchers in NASA Lewis Research Center s Electron Device Technology Branch are developing transmission lines for radiofrequency and wireless circuits that are more efficient, smaller, and make lower cost circuits possible. Traditionally, radiofrequency and wireless circuits have employed a microstrip or coplanar waveguide to interconnect the various electrical elements that comprise a circuit. Although a coplanar waveguide (CPW) is widely viewed as better than a microstrip for most applications, it too has problems. To solve these problems, NASA Lewis and the University of Michigan developed a new version of a coplanar waveguide with electrically narrow ground planes. Through extensive numerical modeling and experimental measurements, we have characterized the propagation constant of the FGC waveguide, the lumped and distributed circuit elements integrated in the FGC waveguide, and the coupling between parallel transmission lines. Although the attenuation per unit length is higher for the FGC waveguide because of higher conductor loss, the attenuation is comparable when the ground plane width is twice the center conductor width as shown in the following graph. An upper limit to the line width is derived from observations that when the total line width is greater than ld/2, spurious resonances due to the parallel plate waveguide mode are established. Thus, the ground plane width must be less than ld/4 where ld is the wavelength in the dielectric. Since the center conductor width S is typically less than l/10 to maintain good transverse electromagnetic mode characteristics, it follows that a ground plane width of B = 2S would also be electrically narrow. Thus, we can now treat the ground strips of the FGC waveguide the same way that the center conductor is treated.

Ponchak, George E.↗

NASA NTRS1995

Adaptive noise reduction circuit for a sound reproduction system

A noise reduction circuit for a hearing aid having an adaptive filter for producing a signal which estimates the noise components present in an input signal. The circuit includes a second filter for receiving the noise-estimating signal and modifying it as a function of a user's preference or as a function of an expected noise environment. The circuit also includes a gain control for adjusting the magnitude of the modified noise-estimating signal, thereby allowing for the adjustment of the magnitude of the circuit response. The circuit also includes a signal combiner for combining the input signal with the adjusted noise-estimating signal to produce a noise reduced output signal.

Engebretson, A. Maynard↗

NASA NTRS1989

Digital first order hold circuit

There is provided a digitally controlled first order hold circuit and waveform synthesizer for digitally controlling the representation of a function over an approximation interval. In accordance with the operation of the invention, the first order hold circuit and waveform generator receives a digital data input signal which contains initial condition data, up/down data, and slope data for the approximation interval. The initial condition data is loaded into an up/down counter which is incremented using counting data at a rate depending on the value of the slope data and in a direction depending on the value of the up-down data. In order to minimize delays arising from data acquistion, two frequency synthesizer circuits are provided such that one frequency synthesizer provides counting data while the other frequency synthesizer receives slope data. During alternating intervals, the other frequency synthesizer circuit provides counting data while the other circuit receives slope data. In addition, long length data input signals covering a plurality of approximation intervals are provided to reduce the demands on a main system central processing unit.

Chan, Fred N.↗