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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Processor Would Find Best Paths On Map

Proposed very-large-scale integrated (VLSI) circuit image-data processor finds path of least cost from specified origin to any destination on map. Cost of traversal assigned to each picture element of map. Path of least cost from originating picture element to every other picture element computed as path that preserves as much as possible of signal transmitted by originating picture element. Dedicated microprocessor at each picture element stores cost of traversal and performs its share of computations of paths of least cost. Least-cost-path problem occurs in research, military maneuvers, and in planning routes of vehicles.

Eberhardt, Silvio P.↗
NASA NTRS1980

The RSZ BASIC programming language manual

The RSZ BASIC interactive language is described. The RSZ BASIC interpreter is resident in the Telemetry Data Processor, a system dedicated to the processing and displaying of PCM telemetry data. A series of working examples teaches the fundamentals of RSZ BASIC and shows how to construct, edit, and manage storage of programs.

Stattel, R. J.↗
NASA NTRS1981

The Control Point Library Building System

The Earth Resources Observation System (EROS) Data Center in Sioux Falls, South Dakota distributes precision corrected Landsat MSS and RBV data. These data are derived from master data tapes produced by the Master Data Processor (MDP), NASA's system for computing and applying corrections to the data. Included in the MDP is the Control Point Library Building System (CPLBS), an interactive, menu-driven system which permits a user to build and maintain libraries of control points. The control points are required to achieve the high geometric accuracy desired in the output MSS and RBV data. This paper describes the processing performed by CPLBS, the accuracy of the system, and the host computer and special image viewing equipment employed.

Niblack, W.↗
NASA NTRS1994

Redundant Buses For Loosely Coupled Dual Computers

Digital electronic network contains two data processors loosely coupled to each other and to four remote terminals via three MIL-STD-1553B data buses. Three-bus configuration provides redundancy for protection against failure of one of the processors and against failures of one or two buses. Triple-bus architecture used for fault tolerance in similar terrestrial digital electronic systems.

Katz, Richard B.↗
NASA NTRS1990

Optimal Allocation Of Tasks In Hypercube Computers

Uniform tasks distributed uniformly or else assigned to one processor. Investigation in theory of scheduling yielded optimal scheme for allocation of tasks among digital data processors in hypercube ensemble. Applies to tasks that require equal time to execute, performed in any order, and between any two of which equal amounts of communication required. Reduces overall processing time for given set of computational tasks.

Salama, Moktar A.↗
NASA NTRS1991

Techniques in processing multi-frequency multi-polarization spaceborne SAR data

This paper presents the algorithm design of the SIR-C ground data processor, with emphasis on the unique elements involved in the production of registered multifrequency polarimetric data products. A quick-look processing algorithm used for generation of low-resolution browse image products and estimation of echo signal parameters is also presented. Specifically the discussion covers: (1) azimuth reference function generation to produce registered polarimetric imagery; (2) geometric rectification to accommondate cross-track and along-track Doppler drifts; (3) multilook filtering designed to generate output imagery with a uniform resolution; and (4) efficient coding to compress the polarimetric image data for distribution.

Curlander, John C.↗
NASA NTRS1993

Runtime support and compilation methods for user-specified data distributions

This paper describes two new ideas by which an HPF compiler can deal with irregular computations effectively. The first mechanism invokes a user specified mapping procedure via a set of compiler directives. The directives allow use of program arrays to describe graph connectivity, spatial location of array elements, and computational load. The second mechanism is a simple conservative method that in many cases enables a compiler to recognize that it is possible to reuse previously computed information from inspectors (e.g. communication schedules, loop iteration partitions, information that associates off-processor data copies with on-processor buffer locations). We present performance results for these mechanisms from a Fortran 90D compiler implementation.

Ponnusamy, Ravi↗
NASA NTRS1992

NASA experimental airborne doppler radar and real time processor for wind shear detection

The topics are presented in viewgraph form and include the following: experimental radar system capabilities; an experimental radar system block diagram; wind shear radar signal and data processor (WRSDP); WRSDP hardware architecture; WRSDP system design goals; DSP software development tools; OS-9 software development tools; WRSDP digital signal processing; WRSDP display operational modes; WRSDP division of functions; structure of WRSDP signal and data processing algorithms; and the wind shear radar flight experiment.

Schaffner, Philip H.↗
NASA NTRS2016

Fast Plasma Investigation for Magnetospheric Multiscale

The Fast Plasma Investigation (FPI) was developed for flight on the Magnetospheric Multiscale (MMS) mission to measure the differential directional flux of magnetospheric electrons and ions with unprecedented time resolution to resolve kinetic-scale plasma dynamics. This increased resolution has been accomplished by placing four dual 180-degree top hat spectrometers for electrons and four dual 180-degree top hat spectrometers for ions around the periphery of each of four MMS spacecraft. Using electrostatic field-of-view deflection, the eight spectrometers for each species together provide 4pi-sr-field-of-view with, at worst, 11.25-degree sample spacing. Energy/charge sampling is provided by swept electrostatic energy/charge selection over the range from 10 eVq to 30000 eVq. The eight dual spectrometers on each spacecraft are controlled and interrogated by a single block redundant Instrument Data Processing Unit, which in turn interfaces to the observatory's Instrument Suite Central Instrument Data processor. This paper described the design of FPI, its ground and in-flight calibration, its operational concept, and its data products.

Pollock, C.↗
NASA NTRS1992

The TOPSAR interferometric radar topographic mapping instrument

The NASA DC-8 AIRSAR instrument was augmented with a pair of C-band antennas displaced across track to form an interferometer sensitive to topographic variations of the Earth's surface. The antennas were developed by the Italian consortium Co.Ri.S.T.A., under contract to the Italian Space Agency (ASI), while the AIRSAR instrument and modifications to it supporting TOPSAR were sponsored by NASA. A new data processor was developed at JPL for producing the topographic maps, and a second processor was developed at Co.Ri.S.T.A. All the results presented below were processed at JPL. During the 1991 DC-8 flight campaign, data were acquired over several sites in the United States and Europe, and topographic maps were produced from several of these flight lines. Analysis of the results indicate that statistical errors are in the 2-3 m range for flat terrain and in the 4-5 m range for mountainous areas.

Zebker, Howard A.↗
NASA NTRS1988

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Mcmillan, Gary B.↗
NASA NTRS1985

Synchronizing Data-Bus Messages

Adapter allows communications among as many as 30 data processors without central bus controller. Adapter improves reliability of multiprocessor system by eliminating point of failure that causes entire system to fail. Scheme prevents data collisions and eliminates nonessential polling, thereby reducing power consumption.

Harris, L. H.↗
NASA NTRS1990

Concurrent Image Processing Executive (CIPE). Volume 2: Programmer's guide

This manual is intended as a guide for application programmers using the Concurrent Image Processing Executive (CIPE). CIPE is intended to become the support system software for a prototype high performance science analysis workstation. In its current configuration CIPE utilizes a JPL/Caltech Mark 3fp Hypercube with a Sun-4 host. CIPE's design is capable of incorporating other concurrent architectures as well. CIPE provides a programming environment to applications' programmers to shield them from various user interfaces, file transactions, and architectural complexities. A programmer may choose to write applications to use only the Sun-4 or to use the Sun-4 with the hypercube. A hypercube program will use the hypercube's data processors and optionally the Weitek floating point accelerators. The CIPE programming environment provides a simple set of subroutines to activate user interface functions, specify data distributions, activate hypercube resident applications, and to communicate parameters to and from the hypercube.

Williams, Winifred I.↗
NASA NTRS1992

A computerized aircraft battery servicing facility

The latest upgrade to the Aerospace Energy Systems Laboratory (AESL) is described. The AESL is a distributed digital system consisting of a central system and battery servicing stations connected by a high-speed serial data bus. The entire system is located in two adjoining rooms; the bus length is approximately 100 ft. Each battery station contains a digital processor, data acquisition, floppy diskette data storage, and operator interfaces. The operator initiates a servicing task and thereafter the battery station monitors the progress of the task and terminates it at the appropriate time. The central system provides data archives, manages the data bus, and provides a timeshare interface for multiple users. The system also hosts software production tools for the battery stations and the central system.

Glover, Richard D.↗
NASA NTRS1993

RADARSAT program

Work on the RADARSAT system is progressing towards the currently scheduled launch date of early 1995. The spacecraft bus and the Synthetic Aperture Radar (SAR) payload are at various stages of development. Requirements for the ground segment have been mostly established. The design of the ground elements such as the mission control facility and the SAR data processor is underway. The SAR applications development work is continuing and the chosen distributor, RADARSAT International Inc. (RSI) is making preparations to market RADARSAT data internationally. A plan for the follow-on to RADARSAT 1 is being finalized to ensure continuity of SAR data under the Radarsat program.

Mcnally, J.↗
NASA NTRS1990

Assignment Of Finite Elements To Parallel Processors

Elements assigned approximately optimally to subdomains. Mapping algorithm based on simulated-annealing concept used to minimize approximate time required to perform finite-element computation on hypercube computer or other network of parallel data processors. Mapping algorithm needed when shape of domain complicated or otherwise not obvious what allocation of elements to subdomains minimizes cost of computation.

Salama, Moktar A.↗
NASA NTRS1974

GSFC magnetic field experiment Explorer 43

The magnetic field experiment flown on Explorer 43 is described. The detecting instrument is a triaxial fluxgate magnetometer which is mounted on a boom with a flipping mechanism for reorienting the sensor in flight. An on-board data processor takes successive magnetometer samples and transmits differences to the telemetry system. By examining these differences in conjunction with an untruncated sample transmitted periodically, the original data may be uniquely reconstructed on the ground.

Seek, J. B.↗
NASA NTRS1972

Polar orbiting operational weather satellites.

The progress in the development of operational weather satellites is reviewed, covering their chronology from Explorer 7 of 1959 through Meteor 12 of June, 1972. Special attention is given to the development of the TIROS series satellites with the evolution of their operational sensors, data systems and performance requirements. The topics also include the data collection system designs, to Advanced Very High Resolution Radiometer (AVHRR), the sounder radiometer, the Solar Environment Monitor (SEM), the data processor, and TIROS-N operation and orbital characteristics. It is expected that TIROS-N and its forthcoming advanced versions will provide an effective technology for sensing environmental data on a global scale in the latter half of the decade.

Stampfl, R. A.↗