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At least 127 records · Page 7

Thomson Scattering Diagnostic Data Acquisition Systems for Modern Fusion Systems

Uniquely designed complex data acquisition system for Thomson scattering diagnostic was developed. It allows recording short duration (3-5 ns) scattered pulses with 2 GHz sampling rate and 10-bit total resolution in oscilloscope mode. The system consists up to 48 photo detector modules with 0- 200 MHz bandwidth, 1-48 simultaneously sampling ADC modules and synchronization subsystem. The photo detector modules are based on avalanche photodiodes (APD) and ultra-low noise trans-impedance amplifiers. ADC modules include fast analog to digital converters and digital units based on the FPGA (Field- Programmable Gate Array) for data processing and storage. The synchronization subsystem is used to form triggering pulses and to organize the simultaneously mode of ADC modules operation. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

High-bandwidth reconfigurable data acquisition card

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Chen, Kai↗

Qualified display system architecture - 246

There is a need in the nuclear industry for a Qualified Display System (QDS) architecture as described in this paper. The function of the QDS is to process and display Regulatory Guide 1.97 post accident monitoring parameters. The QDS is implemented on the Lockheed Martin Field-Programmable Gate Array (FPGA) based Nuclear Protection and Control (NuPAC) digital platform, coupled with a Qualified Display Controller (QDC) and a Safety Display Unit (SDU). The QDS is designed to meet the requirements of IEEE 603-1991 (endorsed by Regulatory Guide 1.153, Rev. 1), IEEE 497-2002 (endorsed by Regulatory Guide 1.97, Rev. 4), and IEEE 7-4.3.2- 2003 (endorsed by Regulatory Guide 1.152, Rev. 3). The QDS is designed with flexibility such that it can be implemented in an advanced reactor design, Small Modular Reactor (SMR) with any cooling medium, or digital upgrade project for an operating nuclear plant. The QDS has four independent and redundant divisions. Each division has five layers in the architecture: Process variable input signals; Process Protection Logic (PPL); Algorithm Logic (AL), Interface Panel (IP); and Safety Display Unit (SDU). The QDS meets the following design criteria: redundancy, independence, predictability and repeatability, and diversity capability. The QDS architecture also meets the simplicity design principle. The QDS architecture design provides flexibility in the implementation in a plant. The QDS can be implemented in the design of a new advanced plant or as a digital upgrade in an operating plant. (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

Practical applications of model checking in the finnish nuclear industry - 281

Model checking is a powerful, formal, computer-assisted verification method that can be used to prove that a model of a (hardware or software) system fulfills stated properties. When used right, model checking can prove the correctness of instrumentation and control (I and C) system application logic, be it a software or a field-programmable gate array (FPGA) based design. The verified properties can also address unwanted functionality, making model checking a very effective method for analyzing spurious actuation. Despite the benefits, model checking is still not widely adopted in the verification of I and C systems, one exception being the Finnish nuclear industry. Since 2008, VTT has applied model checking in practical customer work related to the Olkiluoto 3 EPR, Loviisa 1 and 2 VVER-440, and Hanhikivi 1 AES-2006 nuclear power plants, on commission from either the regulator or the utilities. In this paper, we look at how the method has been used in each of these three projects. We also introduce a user-friendly, graphical modelling tool called MODCHK. We then present an overall view of the design issues detected during nine years of customer work, and one practical example. The 100% coverage means that the design errors that are found often relate to scenarios that are otherwise hard to account for (e.g., exact timing of events, or improper operator actions). (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗

A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.

do Amaral Custodio, Paulo Vitor↗

SQuaD: Smart Quantum Detection for Photon Recognition and Dark Count Elimination

Quantum detectors of single photons are an essential component for quantum information processing across computing, communication and networking. Today's quantum detection system, which consists of single photon detectors, timing electronics, control and data processing software, is primarily used for counting the number of single photon detection events. However, it is largely incapable of extracting other rich physical characteristics of the detected photons, such as their wavelengths, polarization states, photon numbers, or temporal waveforms. This work, for the first time, demonstrates a smart quantum detection system, SQuaD, which integrates a field programmable gate array (FPGA) with a neural network model, and is designed to recognize the features of photons and to eliminate detector dark-count. The SQuaD is a fully integrated quantum system with high timing-resolution data acquisition, onboard multi-scale data analysis, intelligent feature recognition and extraction, and feedback-driven system control. Our \name experimentally demonstrates 1) reliable photon counting on par with the state-of-the art commercial systems; 2) high-throughput data processing for each individual detection events; 3) efficient dark count recognition and elimination; 4) up to 100% accurate feature recognition of photon wavelength and polarization. Additionally, we deploy the SQuaD to an atomic (erbium ion) photon emitter source to realize noise-free control and readout of a spin qubit in the telecom band, enabling critical advances in quantum networks and distributed quantum information processing.

Linne, Karl C. [U. Chicago (main)] (ORCID:00090009↗

Advancing \textit{otsdaq}: Enhancements for Usability, Accuracy, and Robustness

High-energy physics (HEP) experiments require data acquisition (DAQ) systems that can orchestrate complex detector operations, high data throughput, and responsive, real-time feedback to operators. Traditional DAQ stacks, which are often bespoke, command-line driven and highly specific, impose large learning curves on users. The Off-The-Shelf Data Acquisition (\textit{otsdaq}) framework was created to address these issues by offering a highly customizable and scalable browser-based ’desktop’ environment, in which experiment-specific control and monitoring applications can be easily deployed and integrated. Although the initial development of the \textit{otsdaq} software was aimed at the Fermilab Test Beam Facility, \textit{otsdaq} is now being leveraged for broader deployment, including the upcoming Mu2e experiment, where real-time monitoring of field-programmable gate array (FPGA)-based Data Transfer Controllers (DTCs), Clock and Fanout (CFO) boards, and several other subsystems are critical. We contribute a set of targeted improvements to \textit{otsdaq}: bitmap visualization functionality for configured data, improved and corrected delta-based DTC throughput metrics, version control (VC)-backed source navigation for console messages, custom navigation hooks to eliminate disruptive user interface glitches, and copy-to-clipboard support for macro execution history. These changes improve usability, reduce debugging time, and increase accuracy in performance data as Mu2e moves toward commissioning.

Mohammed, A. [Unlisted, US]↗

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Qubit Control System (QubiC) v1.0

We design a modular FPGA (field-programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software.

Huang, Gang↗

Analysis, optimization, and implementation of a hybrid DS/FFH spread-spectrum technique for smart grid communications

In recent years, there has been great interest in using hybrid spread-spectrum (HSS) techniques for commercial applications, particularly in the Smart Grid, in addition to their inherent uses in military communications. This is because HSS can accommodate high data rates with high link integrity, even in the presence of significant multipath effects and interfering signals. A highly useful form of this transmission technique for many types of command, control, and sensing applications is the specific code-related combination of standard direct sequence modulation with fast frequency hopping, denoted hybrid DS/FFH, wherein multiple frequency hops occur within a single data-bit time. In this paper, error-probability analyses are performed for a hybrid DS/FFH system over standard Gaussian and fading-type channels, progressively including the effects from wide- and partial-band jamming, multi-user interference, and varying degrees of Rayleigh and Rician fading. In addition, an optimization approach is formulated that minimizes the bit-error performance of a hybrid DS/FFH communication system and solves for the resulting system design parameters. The optimization objective function is non-convex and can be solved by applying the Karush-Kuhn-Tucker conditions. We also present our efforts toward exploring the design, implementation, and evaluation of a hybrid DS/FFH radio transceiver using a single FPGA. Numerical and experimental results are presented under widely varying design parameters to demonstrate the adaptability of the waveform for varied harsh smart grid RF signal environments.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micro-Mesh Gaseous Structure (Micromegas) detector of the ATLAS New Small Wheel (NSW) upgrade. The Address in Real Time (ART) signals are generated by the front-end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit-selection. The processed data from the ART ASIC will be transmitted out of the NSW through the GBTx serializer, the unidirectional Versatile Twin Transmitter (VTTx) and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FPGA Mezzanine Card (FMC) based testing platform and a special designed firmware/software are developed. We find that this test platform works with the commercial Xilinx VC707 FPGA development kit, independent of the other electronics of the NSW it can test all the functions of the ADDC and its long-term stability. This paper will introduce the design, testing procedure and results of the ADDC and the FMC testing platform.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

A PIPS + SrI 2 (Eu) detector for atmospheric radioxenon monitoring

The PIPS–SrI 2 (Eu) is a prototype atmospheric radioxenon detection system designed at Oregon State University in support of international efforts towards monitoring clandestine nuclear weapon testing activities. This detector aims to address some shortcomings found in currently deployed beta–gamma atmospheric radioxenon detection systems, such as lackluster energy resolution and memory effect, by employing modern detection materials and readout. The system uses a PIPSBox, a silicon-based gas cell, for electron detection, and a pair of ultrabright, D-shaped SrI 2 (Eu) scintillators coupled to silicon photomultipliers for photon detection. A custom eight-channel digital pulse processor equipped with a field programmable gate-array (FPGA) identifies electron–photon coincidences between the volumes in near real-time. Gas samples of the four radioxenon isotopes of interest were independently measured with the PIPS–SrI 2 (Eu) detection system to determine energy resolution and efficiency. Application of FPGA-based coincidence discrimination in near real-time reduced the ambient background count rate by 95.85 ± 0.04%. Using parameters from the Xenon International gas processing unit and assuming a blank sample and zero memory effect the minimum detectable concentrations (MDCs) for the isotopes were calculated to be 0.12 ± 0.03, 0.27 ± 0.05, 0.15 ± 0.02, and 1.00 ± 0.08 mBq/m 3 air for 131m Xe, 133 Xe, 133m Xe, and 135 Xe, respectively. These MDC estimates compare well with other radioxenon detection systems employed in the International Monitoring System (IMS) and indicate that the PIPS–SrI 2 (Eu) is in compliance with the Comprehensive Nuclear Test-Ban-Treaty Organization (CTBTO) sensitivity requirement of ≤ 1 mBq/m 3 for 133 Xe.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability from an application point-of-view.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

The continuous readout stream of the MicroBooNE liquid argon time projection chamber for detection of supernova burst neutrinos

The MicroBooNE continuous readout stream is a parallel readout of the MicroBooNE liquid argon time projection chamber (LArTPC) which enables detection of non-beam events such as those from a supernova neutrino burst. The low energies of the supernova neutrinos and the intense cosmic-ray background flux due to the near-surface detector location makes triggering on these events very challenging. Instead, MicroBooNE relies on a delayed trigger generated by SNEWS (the Supernova Early Warning System) for detecting supernova neutrinos. The continuous readout of the LArTPC generates large data volumes, and requires the use of real-time compression algorithms (zero suppression and Huffman compression) implemented in an FPGA (field-programmable gate array) in the readout electronics. In this paper we present the results of the optimization of the data reduction algorithms, and their operational performance. To demonstrate the capability of the continuous stream to detect low-energy electrons, a sample of Michel electrons from stopping cosmic-ray muons is reconstructed and compared to a similar sample from the lossless triggered readout stream.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage Applications

In common digital electronics design practice, combinatorial loop is less preferable, especially in the multi-bit cases. An exception of multi-bit feedback system that is allowed to be implemented in combinatorial loop is the Gray code sequence generator. The Gray code sequence generator runs by itself without being driven by an external clock. It steps through Gray code sequence significantly faster than the Gray code counter under the same silicon technology. In high energy physics experiments, it is necessary to find a low resource usage and low power TDC (Time-to-Digital-Converter) scheme for high channel count detectors. A Gray code oscillator based TDC is a good candidate for such a scheme. In this paper, we describe our work of design and implementation of a TDC based on combinatorial Gray code oscillator in a Xilinx Kintex-7 FPGA (Field-Programmable Gate Array). The implementation and test results are presented. The test result shows that the TDC using only 8 logic elements is able to reach a RMS precision of 160 ps for time difference measurements of a single pulse. The single pulse measurement precision can be further improved to 51 ps with the weighted average scheme using data from the same TDC channels captured by 4 consecutive system clock edges.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗