Search NASA⌕ Search

SEARCH · Search NASA

Results for “LOGIC CIRCUIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Integrated-Circuit Pseudorandom-Number Generator

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

Steelman, James E.↗
NASA NTRS1984

Finding Open Faults In CMOS Circuits

Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.

Chandramouli, R.↗
NASA NTRS2003

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Kaplan, Steven B.↗
NASA NTRS1972

Batch fabrication process development for ferrite logic conductors

A process for fabricating ultrareliable magnetic ferrite logic circuits is described in which the conductors are formed by a combination of two batch type processes - photolithography and electroplating - and a mechanized writing process for completing conductors in the third dimension. Up to 4 turns, through an aperture 1 mm in diameter, are formed by the described process. The number of joints in the conductors is reduced by use of this process to only those which are required for input, output and power connections of a logic block. To demonstrate feasibility, 8-stage magnetic ring counter circuits have been fabricated.

Heckler, C. H., Jr.↗
NASA NTRS1994

A programmable heater control circuit for spacecraft

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Nguyen, D. D.↗
NASA NTRS1973

Lightning tracking system

A system is described for locating lightning strikes by developing the coordinates of a pair of lines, each of which is produced at a reference sensing station. At each station there are a pair of directional antennas which produce analog signals responsive to a lightning stroke. These analog signals are fed to a pair of integrators which integrate the signals for a predetermined period of time so as to produce the X and Y coordinate of a particular line. The analog signals are also fed through a square rooter, a Schmitt trigger circuit, and flip-flops to produce pulses for starting and stopping the integrators. The system at the remote station is similar to that at the central station and is tied to the circuitry at the central station through logic circuits to minimize the chance of error from spurious signals. Computers, printers, and plotters are utilized to plot the exact location of the lightning stroke.

Wojtasinski, R. J.↗
NASA NTRS1976

Console test report for shuttle task 501 shuttle carrier aircraft transceiver console (SED 36115353-301)

Performance tests completed on the Space Shuttle Carrier Aircraft (SCA) transceiver console, verifying its design objectives, were described. These tests included: (1) check of power supply voltages for correct output voltage and energization at the proper point in the turn on sequence, (2) check of cooling system (LRU blower, overload sensors and circuitry, and thermocouple probe), (3) check of control circuits logic, including the provisions for remote control and display, (4) check of the LRU connector for presence of correct voltages and absence of incorrect voltages under both energized and deenergized conditions, and (5) check of the AGC and power output monitor circuits.

Lane, J. H.↗
NASA NTRS2004

Ultralow-Power Digital Correlator for Microwave Polarimetry

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Piepmeier, Jeffrey R.↗
NASA NTRS1975

A system for multichannel recording and automatic reading of information

A system for the recording and processing of telescope data is considered for measurements of EW asymmetry. The information is recorded by 45 channels on a continuously moving 35-mm film. The dead time of the recorder is about 0.1 sec. A sorting electronic circuit is used to reduce the errors when the statistical time distribution of the pulses is recorded. The recorded information is read out by means of photoresistors. The phototransmitter signals are fed either to the mechanical recorder unit for preliminary processing, or to a logical circuit which controls the operation of the punching device. The punched tape is processed by an electronic computer.

Bogomolov, E. A.↗
NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗
NASA NTRS1989

Multi-port, optically addressed RAM

A random access memory addressing system utilizing optical links between memory and the read/write logic circuits comprises addressing circuits including a plurality of light signal sources, a plurality of optical gates including optical detectors associated with the memory cells, and a holographic optical element adapted to reflect and direct the light signals to the desired memory cell locations. More particularly, it is a multi-port, binary computer memory for interfacing with a plurality of computers. There are a plurality of storage cells for containing bits of binary information, the storage cells being disposed at the intersections of a plurality of row conductors and a plurality of column conductors. There is interfacing logic for receiving information from the computers directing access to ones of the storage cells. There are first light sources associated with the interfacing logic for transmitting a first light beam with the access information modulated thereon. First light detectors are associated with the storage cells for receiving the first light beam, for generating an electrical signal containing the access information, and for conducting the electrical signal to the one of the storage cells to which it is directed. There are holographic optical elements for reflecting the first light beam from the first light sources to the first light detectors.

Johnston, Alan R.↗
NASA NTRS1991

Method and apparatus for eliminating unsuccessful tries in a search tree

A circuit switching system in an M-ary, n-cube connected network completes a best-first path from an originating node to a destination node by latching valid legs of the path as the path is being sought out. Each network node is provided with a routing hyperswitch sub-network, (HSN) connected between that node and bidirectional high capacity communication channels of the n-cube network. The sub-networks are all controlled by routing algorithms which respond to message identification headings (headers) on messages to be routed along one or more routing legs. The header includes information embedded therein which is interpreted by each sub-network to route and historically update the header. A logic circuit, available at every node, implements the algorithm and automatically forwards or back-tracks the header in the network legs of various paths until a completed path is latched.

Peterson, John C.↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
DOE OSTI2024

Point containment algorithms for constructive solid geometry with unbounded primitives

Here, we present several algorithms for evaluating point containment in constructive solid geometry (CSG) trees with unbounded primitives. Three algorithms are presented based on postfix, prefix, and infix notations of the CSG binary expression tree. We show that prefix and infix notations enable short-circuiting logic, which reduces the number of primitives that must be checked during point containment. To evaluate the performance of the algorithms, each algorithm was implemented in the OpenMC Monte Carlo particle transport code, which relies on CSG to represent solid bodies through which subatomic particles travel. Two sets of tests were carried out. First, the execution time to generate a rasterized image of a 2D slice of three CSG models of varying complexity was measured. Use of both prefix and infix notations offered significant speedup over the postfix notation that has traditionally been used in particle transport codes, with infix resulting in a 6 x reduction in execution time relative to postfix for a model of a tokamak fusion device. We then measured the execution time of neutron transport simulations of the same three models using each of the algorithms. The results and performance improvements reveal the same trends as for the rasterization test, with a 5.52 x overall speedup using the infix notation relative to the original postfix notation in OpenMC for the tokamak model.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics

Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm -2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS 2 transistors exhibiting high on/off current ratios over 10 8 , ultralow subthreshold swing of 65 mV dec -1 and ultralow leakage current density of ~10 -6 A cm -2 . Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor–insulator transition at the clean-limit Bi 2 Sr 2 CaCu 2 O 8+δ can also be realized through fluoride gating. In conclusion, our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Integrating magnetic Co-nanopillars in a NbN-based VAN thin film as a multifunctional hybrid metamaterial

NbN thin films are considered as a promising alternative candidate to conventional Al superconducting electrodes for Josephson junction devices, superconducting qubits and quantum logic circuits. Herein, by co-growing ferromagnetic Co with superconducting NbN, self-assembled NbN–Co vertically aligned nanocomposite (VAN) thin films have been successfully deposited on a MgO substrates, with NbN in its cubic superconducting phase. The obtained VAN metamaterials exhibit epitaxial growth of NbN with uniformly dispersed Co nanoplates. Further physical property characterization reveals that the NbN–Co VAN presents ferromagnet properties with strong out-of-plane magnetic anisotropy and optical anisotropy. This hybrid metamaterial system could find future applications in superconducting spintronic devices and quantum computing devices.

Zhang, Yizhi [Purdue Univ., West Lafayette, IN (Un↗
DOE OSTI2025

InAs sidewall tunnel diodes enabled by surface states

Negative differential resistance (NDR), where the device current decreases with increasing bias voltage, is a representative phenomenon where quantum mechanics induces counterintuitive physical behavior and offers promising applications such as high-frequency oscillators, amplifiers, and multilevel logic circuits. While the NDR behavior has been extensively studied in various materials and devices, the role of surface properties in NDR, particularly in InAs-based diodes, remains underexplored. In this work, we report the observation of NDR in vertically structured InAs p + n diodes that exhibit a peak-valley current ratio of ∼6, which is suitably high for applications. Circumference-normalized current–voltage characterization revealed that the NDR originates from band-to-band tunneling between the valence band of p + -InAs and the conduction band of an n + -InAs surface, where the n + surface is due to surface states on otherwise n − -InAs. In addition, by comparing devices with various surface passivation methods (without intentional passivation, benzocyclobutene polymer, and silicon nitride), we found that the surface termination significantly affects the NDR characteristics. We present an equivalent circuit model to explain the observed device behavior. These findings offer insights into surface-enabled NDR phenomena and present new knobs for engineering NDR devices.

Circuit theorems↗