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Skew test data are presented on a tape recorder transport with a double capstan drive for a 100 KHz tone recorded on five tracks simultaneously. Phase detectors were used to measure the skew when the center channel was the 100 KHz reference.
System, fabricated of highly-reliable digital logic elements, operates on binary pulse-code-modulated signals and derives internal synchronization from data signal. All-digital implementation of detector develops synchronization from data signal by computer cross-correlation of command modulation signal with its expected forms in sequence and adjusts detector phases in accordance with correlation peaks.
An electronic filter is described which simultaneously maintains a constant bandwidth and a constant center frequency gain as the input signal frequency varies, and remains self-tuning to that center frequency over a decade range. The filter utilizes a field effect transistor (FET) as a voltage variable resistance in the bandpass frequency determining circuit. The FET is responsive to a phase detector to achieve self-tuning.
Digital multiplication of two waveforms using delta modulation (DM) is discussed. It is shown that while conventional multiplication of two N bit words requires N2 complexity, multiplication using DM requires complexity which increases linearly with N. Bounds on the signal-to-quantization noise ratio (SNR) resulting from this multiplication are determined and compared with the SNR obtained using standard multiplication techniques. The phase locked loop (PLL) system, consisting of a phase detector, voltage controlled oscillator, and a linear loop filter, is discussed in terms of its design and system advantages. Areas requiring further research are identified.
Modified phase-locked loop (PLL) generates clock from incoming data signal. To minimize effects of threshold phase-detector gain variations, the PLL uses a dither oscillator, a dither band-pass filter, and correlator instead of coherent amplitude detector.
A new type of phase detector for pseudonoise code tracking is introduced and analyzed in comparison with the delay lock loop (DLL) and tau-dither loop (TDL) configurations. It is shown that the double dither loop (DDL) combines the best features of the DLL and the TDL in that the DDL is insensitive to gain and offset imbalances and does not suffer the 3-dB degradation in noise performance typically associated with the TDL. The double dither concept is applicable to other dual channel detectors such as in a Costas-type carrier tracking loop.
A cesium beam frequency standards for spaceflight application on Navigation Development Satellites was designed and fabricated and preliminary testing was completed. The cesium standard evolved from an earlier prototype model launched aboard NTS-2 and the engineering development model to be launched aboard NTS satellites during 1979. A number of design innovations, including a hybrid analog/digital integrator and the replacement of analog filters and phase detectors by clocked digital sampling techniques are discussed. Thermal and thermal-vacuum testing was concluded and test data are presented. Stability data for 10 to 10,000 seconds averaging interval, measured under laboratory conditions, are shown.
Stable frequency sources and signal processing blocks were characterized by their noise spectra, both discrete and random, in the frequency domain. Conventional measures are outlined, and systems for performing the measurements are described. Broad coverage of system configurations which were found useful is given. Their functioning and areas of application are discussed briefly. Particular attention is given to some of the potential error sources in the measurement procedures, system configurations, double-balanced-mixer-phase-detectors, and application of measuring instruments.
Feedback circuit controls fluctuations in speed of synchronous ac motor. Voltage proportional to phase angle is developed by phase detector, rectified, amplified, compared to threshold, and reapplied positively or negatively to motor excitation circuit. Speed control reduces wow and flutter of audio turntables and tape recorders, and enhances hunting in gyroscope motors.
A power factor type motor controller is disclosed in which the conventional power factor constant voltage command signal is replaced during a starting interval with a graduated control voltage. This continuation-impart of a pending patent application (Serial No. 199, 765: Three Phase Factor Controller) provides a means for modifying the operation of the system for a motor start-up interval of 5 to 30 second. Using a ramp generators, an initial ramp-like signal replaces a constant power factor signal supplied by a potentiometer. The ramp-like signal is applied to a 15 terminal where it is summed with an operating power factor signal from phase detectors in order to obtain a control signal for ultimately controlling SCR devices. The SCR devices are turned on at an advancing rate with time responsive to the combination signal described rather than simply a function of a ramp-like signal alone.
A discriminator aided technique for acquisition of phase lock to a suppressed carrier signal utilizes a Costas loop which is initially operated open loop and control voltage for its VCXO is derived from a phase detector that compares the VCXO to a reference frequency thus establishing coarse frequency resolution with the received signal. Then the Costas loop is closed with the low-pass filter of the channel having a bandwidth much greater (by a factor of about 10) than in the I channel so that a frequency discriminator effect results to aid carrier resolution. Finally, after carrier acquisition, the Q-channel filter of the Costas loop is switched to a bandwidth substantially equal to that of the I-channel for carrier tracking.
A circuit level analysis for residual carrier tracking of a deep space network signal by a proposed Block V receiver as conceived by the Receiver Advanced Development Team is presented. The objective is to aid the circuit designer in selection of loop parameters to achieve the required performance objectives. The topics specifically addressed are: (1) loop stability and gain requirements, (2) loop component parametric equations, and (3) phase detector technology.
The design of an integrated modem/codec unit which can receive coded and uncoded BPSK an QPSK using de facto standard coding schemes as well as 8PSK-TCM and 16PSK-TCM is examined. The design is totally compatible with today's modulation schemes and capable of processing tomorrow's TCM codes. This is accomplished in the modem by using quadrature channel carrier recovery processing and a version of the MAP phase detector algorithm. The symbol synchronization is accomplished with a derivative of an early-late gate designed to accommodate multilevel signals.
Computer simulated noise performance of the symbol synchronizer loop (SSL) in the Block 5 receiver is compared with the theoretical noise performance. Good agreement is seen at the higher loop SNR's (SNR(sub L)'s), with gradual degradation as the SNR(sub L) is decreased. For the different cases simulated, cycle slipping is observed (within the simulation time of 10(exp 4) seconds) at SNR(sub L)'s below different thresholds, ranging from 6 to 8.5 dB, comparable to that of a classical phase-locked loop. An important point, however, is that to achieve the desired loop SNR above the seemingly low threshold to avoid cycle slipping, a large data-to-loop-noise power ratio, P(sub D)/(N(sub 0)B(sub L)), is necessary (at least 13 dB larger than the desired SNR(sub L) in the optimum case and larger otherwise). This is due to the large squaring loss (greater than or equal to 13 dB) inherent in the SSL. For the special case of symbol rates approximately equaling the loop update rate, a more accurate equivalent model accounting for an extra loop update period delay (characteristic of the SSL phase detector design) is derived. This model results in a more accurate estimation of the noise-equivalent bandwidth of the loop.
Phase-shifted, laser feedback interferometry is a new diagnostic tool developed at the NASA Lewis Research Center under the Advanced Technology Development (ATD) Program directed by NASA Headquarters Microgravity Research Division. It combines the principles of phase-shifting interferometry (PSI) and laser-feedback interferometry (LFI) to produce an instrument that can quantify both optical path length changes and sample reflectivity variations. In a homogenous medium, the optical path length between two points is the product of the index of refraction and the geometric distance between the two points. LFI differs from other forms of interferometry by using the laser as both the source and the phase detector. In LFI, coherent feedback of the incident light either reflected directly from a surface or reflected after transmission through a region of interest will modulate the output intensity of the laser. The combination of PSI and LFI has produced a robust instrument, based on a low-power helium-neon (HeNe) gas laser, with a high dynamic range that can be used to measure either static or oscillatory changes of the optical path length. Small changes in optical path length are limited by the fraction of a fringe that can be measured; we can measure nonoscillatory changes with a root mean square (rms) error of the wavelength/1000 without averaging.
A hot gas turbine engine capacitive probe clearanceometer is employed to measure the clearance gap or distance between blade tips on a rotor wheel and its confining casing under operating conditions. A braze sealed tip of the probe carries a capacitor electrode which is electrically connected to an electrical inductor within the probe which is inserted into a turbine casing to position its electrode at the inner surface of the casing. Electrical power is supplied through a voltage controlled variable frequency oscillator having a tuned circuit in which the probe is a component. The oscillator signal is modulated by a change in electrical capacitance between the probe electrode and a passing blade tip surface while an automatic feedback correction circuit corrects oscillator signal drift. A change in distance between a blade tip and the probe electrode is a change in capacitance therebetween which frequency modulates the oscillator signal. The modulated oscillator signal which is then processed through a phase detector and related circuitry to provide an electrical signal is proportional to the clearance gap.
A power factor type motor controller in which the conventional power factor constant voltage command signal is replaced during a starting interval with a graduated control voltage. The present invention adds to the three-phase system of pending application Ser. No. 199,765, filed Oct. 23, 1980, means for modifying the operation of the system for a motor start-up interval of 5 to 30 seconds. The modification is that of providing via ramp generator 174 an initial ramp-like signal which replaces a constant power factor signal supplied by potentiometer 70. The ramp-like signal is applied to terminal 40 where it is summed with an operating power factor signal from phase detectors 32, 34, and 36 to thereby obtain a control signal for ultimately controlling SCR devices 12, 14, and 16 to effect a gradual turn-on of motor 10. The significant difference of the present invention over prior art is that the SCR devices are turned on at an advancing rate with time responsive to the combination signal described rather than simply a function of a ramp-like signal alone. The added signal, the operating power factor signal, enables the production of a control signal which effectively eliminates a prior problem with many motor starting circuits, which is that of accompanying motor instabilities.
This is a talk given at Computers in High Energy Physics in Adelaide, South Australia, Australia in November 2019. It is partially intended to explain the context of DUNE Computing for computing specialists. The DUNE collaboration consists of over 180 institutions from 33 countries. The experiment is in preparation now with commissioning of the first 10kT fiducial volume Liquid Argon TPC expected over the period 2025-2028 and a long data taking run with 4 modules expected from 2029 and beyond. An active prototyping program is already in place with a short test beam run with a 700T, 15,360 channel prototype of single-phase readout at the neutrino platform at CERN in late 2018 and tests of a similar sized dual-phase detector scheduled for mid-2019. The 2018 test beam run was a valuable live test of our computing model. The detector produced raw data at rates of up to ~2GB/s. These data were stored at full rate on tape at CERN and Fermilab and replicated at sites in the UK and Czech Republic. In total 1.2 PB of raw data from beam and cosmic triggers were produced and reconstructed during the six week test beam run. Baseline predictions for the full DUNE detector data, starting in the late 2020's are 30-60 PB of raw data per year. In contrast to traditional HEP computational problems, DUNE's Liquid Argon TPC data consist of simple but very large (many GB) 2D data objects which share many characteristics with astrophysical images. This presents opportunities to use advances in machine learning and pattern recognition as a frontier user of High Performance Computing facilities capable of massively parallel processing.