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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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DOE OSTI2026

Enhanced Simulation Tools for Scheduling Solar Plus Storage Power Plants

This is the final technical report for the Department of Energy's Office of Energy Efficiency and Renewable Energy (EERE) under the Solar Energy Technology's Office Balance of Systems program, Award Number 38429. This report summarizes the key outputs and findings of the project, which was focused on long-duration energy storage (LDES) and solar. In particular, one of the most significant challenges of maximizing the value of variable solar energy is the timing of charging and discharging stored energy from LDES devices. Power systems often fail to capture the benefits of LDES and can undervalue the role of storage in providing energy arbitrage, reliability support, and resiliency. This project examined those challenges and proposed alternative methodologies that better capture the value that LDES can provide.

14 SOLAR ENERGY↗
DOE OSTI2023

Improving the Quality of Geothermal Data Through Data Standards and Pipelines Within the Geothermal Data Repository: Preprint

For machine learning outputs to be applicable to real world problems, high quality data are needed to ensure high quality results. With the more recent emphasis on machine learning in geothermal, there is an increasing need for greater focus on the quality of the data available for use in these projects. For example, Geothermal Operational Optimization Using Machine Learning (GOOML) utilized large quantities of geothermal power plant operational data to inform power plant operational configurations to maximize power generation. High quality datasets result from dependable sensors or devices collecting data, high frequency of measurements, sufficient data points, adequate metadata, reliable storage of data, and sufficient data curation. Another component that contributes to high quality data is reusability, which can be enhanced through data standardization. Data Standardization creates consistency in formatting and contents of like datasets, lessening preprocessing requirements and ensuring adequate information provided by a given dataset. The Geothermal Data Repository (GDR) aims to help improve data quality through automated data standardization for high-value datasets through the implementation of data pipelines alongside reliable and accessible long-term storage for datasets. As such, the GDR has decided to shift away from recommending the use of Excel-based content models and towards the implementation of automated data pipelines. This takes the burden of data standardization off the user and project team and will increase the availability of standardized geothermal data available through the GDR. A set of recommendations, or a data standard for each data type will exist with each data pipeline in order to advise data collection for maximum usability for future research. This paper serves to describe the GDR's proposed transition towards data standardization through automated data pipelines, to discuss the need for and value of such a shift, and to call for suggestions from the community regarding the most useful data standards and pipelines.

data↗
DOE OSTI2023

Plasma-jet printing of colloidal thermoelectric Bi 2 Te 3 nanoflakes for flexible energy harvesting

Thermoelectric generators (TEGs) convert temperature differences into electrical power and are attractive among energy harvesting devices due to their autonomous and silent operation. While thermoelectric materials have undergone substantial improvements in material properties, a reliable and cost-effective fabrication method suitable for microgravity and space applications remains a challenge, particularly as commercial space flight and extended crewed space missions increase in frequency. This paper demonstrates the use of plasma-jet printing (PJP), a gravity-independent, electromagnetic field-assisted printing technology, to deposit colloidal thermoelectric nanoflakes with engineered nanopores onto flexible substrates at room temperature. We observe substantial improvements in material adhesion and flexibility with less than 2% and 11% variation in performance after 10 000 bending cycles over 25 mm and 8 mm radii of curvature, respectively, as compared to previously reported TE films. Our printed films demonstrate electrical conductivity of 2.5 × 10 3 S m -1 and a power factor of 70 μW m -1 K -2 at room temperature. To our knowledge, these are the first reported values of plasma-jet printed thermoelectric nanomaterial films. This advancement in plasma jet printing significantly promotes the development of nanoengineered 2D and layered materials not only for energy harvesting but also for the development of large-scale flexible electronics and sensors for both space and commercial applications.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2022

Inverter Reliability Estimation for Advanced Inverter Functionality

In the near future, grid operators are expected to regularly use advanced distributed energy resource (DER) functions, defined in IEEE 1547-2018, to perform a range of grid-support operations. Many of these functions adjust the active and reactive power of the device through commanded or autonomous modes, which will produce new stresses on the grid-interfacing power electronics components, such as DC/AC inverters. In previous work, multiple DER devices were instrumented to evaluate additional component stress under multiple reactive power setpoints. We utilize quasi-static time-series simulations to determine voltage-reactive power mode (volt-var) mission profile of inverters in an active power system. Mission profiles and loss estimates are then combined to estimate the reduction of the useful life of inverters from different reactive power profiles. It was found that the average lifetime reduction was approximately 0.15% for an inverter between standard unity power factor operation and the IEEE 1547 default volt-var curve based on thermal damage due to switching in the power transistors. For an inverter with an expected 20-year lifetime, the 1547 volt-var curve would reduce the expected life of the device by 12 days. This framework for determining an inverter's useful life from experimental and modeling data can be applied to any failure mechanism and advanced inverter operation.

component degradation↗
DOE OSTI2025

R&D Program for HEP High-Power Targets at Fermilab

A high-power target system is a key beam element to complete future High Energy Physics (HEP) experiments. In the recent past, major accelerator facilities have been limited in beam power not by their accelerators, but by the beam intercepting device survivability. The target must then endure high power pulsed beam, leading to high cycle thermal stresses/pressures and thermal shocks. The increased beam power will also create significant challenges such as corrosion and radiation damage that can cause harmful effects on the material and degrade their mechanical and thermal properties during irradiation. This can eventually lead to the failure of the material and drastically reduce the lifetime of targets and beam intercepting devices. In order to operate reliable beam-intercepting devices in the framework of energy and intensity increase projects of the future, it is essential to develop a strong R&D program and have synergy with various expertise. After presenting the high power targetry challenges facing next generation multi-MW accelerators, we will give an overview of Fermilab’s R&D program in support of High Power Targetry development. The RaDIATE collaboration (Radiation Damage In Accelerator Target Environment), managed by Fermilab, also draws on existing expertise in related fields to execute a coordinated strategy for high power targetry R&D between the 14 international member institutions.

Pellemoine, Frederique [Fermilab]↗
DOE OSTI2025

Real-Time Lifetime Prediction of Semiconductor Devices Using Hardware-in-the-Loop

This paper presents a unique approach to enable real-time lifespan prediction of semiconductor power modules using a Hardware-in-the-Loop (HIL) system. By integrating the module's overall loss characteristics-specifically switching and conduction losses-with a thermoelectric model of the thermal management system, this research demonstrates that the model can dynamically estimates the junction temperature profile of the semiconductor devices in response to a changing torque demand profile for the motor drive system. This capability enables continuous monitoring of the module's operational time and cumulative stress induced on the devices to compute accumulated remaining lifetime or time-to-failure (TTF). This study provides an architectural framework for the HIL system with high-fidelity component models of multiple physical domains, allowing simulation of dynamic behaviors of a closely-coupled motor drive system. The advanced real-time computation and measurement functionalities of the HIL system allow for both dynamic lifetime calculations based on simulated data and aggregate lifetime predictions utilizing historical data. Moreover, this paper details an algorithm that not only computes cumulative damage but also synthesizes these data into a comprehensive aggregated lifetime metric. This methodology can enhance the maintenance scheduling strategies and operational reliability of semiconductor devices in critical applications, ultimately extending their service life while optimizing performance.

hardware-in-the-loop (HIL)↗
DOE OSTI2023

Automated Design-for-Reliability of a Power Electronics Module

The design of a power electronics module is a multiphysics problem and involves electrical, thermal, and reliability targets and constraints. Although the electrical and thermal design consider multiple aspects such as materials, geometry, and energy losses, reliability design is often limited to the selection of the attachment materials and electrical interconnect types. In this paper, we incorporate reliability metrics in the design phase by investigating the impact of package geometry on the thermomechanical behavior of the die-attachment material. To this end, we conducted thermal and power cycling simulations of a commercial six-pack power module with silicon carbide devices to compute junction temperature and strain energy density per cycle, respectively. We performed multiple simulations with different geometric dimensions and established a correlation between input features and output variables using subspace-based dimension reduction. The machine learning-based dimension reduction method serves as a surrogate model, which can be employed to identify the optimal module design from a thermal and reliability standpoint.

design-for-reliability↗
DOE OSTI2023

Impact of Spatial Variation in Flexibility on System Operations in Electric Power Systems

With the expansion of renewable energy resources in the electric power systems, having flexibility in the setup will allow to maintain the system's reliability and prevailing operations. Such flexibility can be extracted from utility operated and/or consumer owned devices, such as, storage devices, electric vehicles, etc. For the demand side, generally consumer preferences, incentives, etc. enact on the availability of the flexibility; besides, both the spatial and temporal dimension dictates the degree of the flexibility. Consequently, the optimal dispatch of the grid resources might appear intractable as the considerable amount of flexibility are obliquely stemming from the ungovernable consumer devices. Thus characterizing the consequences of diverged feasible flexibility in the system is crucial for operations. In this paper, a procedure is developed to quantify the degree of flexibility of power systems in terms of resource dispatch reconfiguration. Specifically, we develop optimization problems to attain equivalent resource configurations for the power systems to evaluate the spatial volatility of the network and asses the flexibility of the system. The developed process is then validated using numerical simulations for IEEE-30 bus test system.

Sadnan, Rabayet↗
DOE OSTI2024

Wide Bandgap Generation (WBGen): Developing the Future Wide Bandgap Power Electronics Engineering Workforce

This Final Technical Report (FTR) summarizes the work conducted at the Center for Power Electronics Systems (CPES) under the Wide-Bandgap Generation (WBGen) fellowship and traineeship program established by the Advanced Manufacturing and Technologies Office (AMMTO) of the U.S. Department of Energy Office of Energy Efficiency and Renewable Energy (EERE) at Virginia Tech, which had as main objective to train the next generation of U.S. citizen power engineers with wide-bandgap (WBG) power semiconductor expertise, with the intent to aid in fulfilling the future workforce needs in this field. The latter was deemed of strategic importance given the fast-paced growth observed—and predicted—in the demand of this technical expertise, whose practitioners have become the enablers and executioners of the electrification transformation process that not just the U.S., but the whole world, is currently undergoing as it seeks for more effective and efficient ways to use energy. As such, the WBGen program set forth to achieve its educational goals, which in addition sought to broaden the range of WBG-based power electronics by conducting research and development on high-efficiency grid apparatus and high-efficiency electrical power systems, and to also enhance the power engineering curriculum by formalizing WBG-oriented design procedures replacing existent yet now obsolete design procedures developed for Silicon (Si) based power electronics. This effort led CPES to spearhead the development of a new major within The Bradley Electrical and Computer Engineering (ECE) Department at Virginia Tech, namely Electronic Power and Energy Systems (EPES), which coalesced power electronics and power systems courses to provide undergraduate students with a strong formation in the power engineering field, while creating a pipeline of graduate students that could pursue the WBG-based curriculum and conduct research at CPES. In all, in what is considered a true success, eight of the twenty WBGen fellows that graduated program were recruited from the ECE department undergraduate cohort. The traineeship emphasized as well, from its beginning, the partnership with industry and national laboratories, which took advantage of the successful industry consortium at CPES that has historically been formed by 80–90 power and energy companies working in close collaboration with the center. This gave WBGen fellows the accessibility and possibility to conduct internships at partner facilities during the summer months, focused solely on the evaluation, testing, and adoption of WBG devices, which were many times tightly related to their respective research work and plans. In addition, WBGen fellows conducted their main research work within the confines of research programs at CPES conducted with these industry partners, providing them with a unique opportunity to develop not just their technical expertise—while advancing their knowledge, but to also learn and practice a slew of skills needed for their professional growth. As such, the fellows tackled a variety of WBG-related research topics, from device reliability and capability aspects as well as packaging and integration, encompassing the use of advanced materials and new structures, current sharing challenges, and insulation systems, to advanced gate-drivers with integrated sensors and protection mechanisms and active current- and voltage-based control, to optimized layouts seeking to maximize the switching and power processing performance of these devices, to power processing solutions adopting Gallium-Nitride (GaN) and Silicon-Carbide (SiC) power semiconductors for a variety of applications; including radiation-hardened converters for space dc distribution systems, direct three-phase ac-to-ac power converters for aerospace systems, dc-ac inverters for automotive traction drives, high-frequency isolated dc-dc battery chargers also for heavy transportation systems, and medium-voltage dc-dc and dc-ac converters for distribution systems and future power grids. The WBGen program ultimately graduated a total of 20 power engineers, all experts on WBG-based power electronics, awarding 18 M.S. and 2 PhD degrees in the process. These fellows, all U.S. citizens, allowed CPES to increase the number of citizens students to 33 % at the peak of the program, as the traineeship made possible the recruitment of talent with more attractive graduate research assistantship (GRA) contracts. Unfortunately, the present U.S. citizen enrollment at CPES has declined back to historic levels—approximately 10 %, as the regular GRA rates are not competitive enough when compared with entry-level industry jobs. In all, WBGen fellows published a total of 7 peer-reviewed journal articles, 44 papers at international technical conferences, made 42 presentations at international technical conferences, and filed 4 invention disclosures and patent applications, which have since then been granted by the U.S. Patent and Trademark Office (USPTO). Their contribution to CPES, Virginia Tech, the United States, and the world, has been significant, and continues to yield results thanks to the exemplary career that the fellows have initiated at many of the partners of the program, which include Wolfspeed, Raytheon Technologies, Infineon, Lockheed Martin, Dominion Energy, Northrop Grumman, Rivian, Aerospace Corporation, Sandia National Laboratory, National Renewable Energy Laboratory, John Hopkins University, and Virginia Tech.

14 SOLAR ENERGY↗
DOE OSTI2024

Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs

This paper evaluates the impact of the fast high gate-voltage screening technique on gate oxide reliability of commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The measurements are conducted on packaged devices with the intent that the results will be applicable to wafer-level screening. The threshold voltage (V th ) of SiC MOSFETs is measured before and after various screening treatments and recovery process. In addition, constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on SiC MOSFETs to obtain the intrinsic lifetime of gate oxide. The objective of this study is to determine the optimal screening conditions and improve screening efficiency without degradation of gate oxide reliability, such as V th shift and reduced oxide intrinsic lifetime. Due to the differences in the gate oxidation process and structural design of SiC planar and trench MOSFETs, the two types of devices exhibit different oxide reliability in the screening process. The recommended screening conditions obtained in this paper reveal that SiC trench MOSFETs can accept higher screening voltages compared to SiC planar MOSFETs. Hence, it can be concluded that more efficient screening techniques can be adopted for SiC MOSFETs with thicker gate oxide to meet the requirements of industrial applications.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Port Impedance Measurement and Current Injection Response Analysis for PLCs

Programmable Logic Controllers (PLCs) are used to control devices throughout the power system since they have fast control capabilities and can utilize multiple types of communication interfaces. Therefore, studying and mitigating their vulnerabilities to electromagnetic pulse is important for the reliability of PLC operations. Here, in this paper, an effective impedance measurement scheme is proposed and demonstrated for three PLCs to estimate their susceptibility to an electromagnetic pulse. The equivalent non-uniform transmission line model is established to eliminate the impact of the fixture in the de-embedding process. Then different parameters of the impedance measurement setup are explored. Based on the measured impedance, the equivalent circuit is established to calculate the response of the device when subjected to the electromagnetic pulse. The voltage and current responses of different interfaces are compared utilizing the developed pulsed Current Injection (CI) method. Finally, the impedance measurement scheme is verified through testing using three measuring instruments. And the CI simulation experiments reveal the characteristics and susceptibilities of different PLCs interfaces, indicating that some protection measures are required for the reliable operation of the PLC.

42 ENGINEERING↗
DOE OSTI2026

Analytic Expressions for Extracting Far Scrape-Off Layer Transport Coefficients from the Plasma-Wall Interaction of Divertor Tokamaks

Magnetic-confinement DT pilot plants and DEMO-class devices will employ thin breeding blanket first walls with substantially lower steady-state power-handling margins than ITER-like thick walls, making reliable prediction of main-chamber particle and heat loads increasingly critical. This report addresses that need by developing analytic tools to interpret far scrape-off layer (far-SOL) plasma–wall interaction measurements in divertor tokamaks, with the goal of extracting effective cross-field transport coefficients from “window-frame” experiments and related diagnostics.

Stangeby, P. C. [Univ. of Toronto, ON (Canada)]↗
DOE OSTI2023

Towards linking lab and field lifetimes of perovskite solar cells

Metal halide perovskite solar cells (PSCs) represent a promising low-cost, thin-film photovoltaic (PV) technology, with unprecedented power conversion efficiencies (PCEs) obtained for both single-junction and tandem applications. To push PSCs toward commercialization, it is critical, albeit challenging, to understand device reliability under real-world outdoor conditions where multiple stress factors (e.g., light, heat, humidity) coexist, generating complicated degradation behaviors. It is necessary to identify accelerated indoor testing protocols - which can correlate specific stressors with observed degradation modes in fielded devices - to quickly guide PSC development. Here, we use a state-of-the-art p-i-n PSC stack (with PCE up to ~25.5%) to show that indoor accelerated stability tests can predict our 6-month outdoor aging tests. Device degradation rates under illumination and at elevated temperatures are most instructive for understanding outdoor device reliability. Further, we also find that the indium tin oxide (ITO)/self-assembled monolayer (SAM)-based hole transport layer (HTL)/perovskite interface most strongly affects our device operation stability. Improving the ion-blocking properties of the SAM HTL increases averaged device operational stability at 50 degree C-85 °C by a factor of ~2.8, reaching over 1000 h at 85 °C and to near 8200 h at 50 °C with a projected 20% degradation, which is among the best to date for high-efficiency p-i-n PSCs.

14 SOLAR ENERGY↗
DOE OSTI2025

Tokamak Disruption Simulation (Final Technical Report)

The Tokamak Disruption Simulation collaboration was a SciDAC (Scientific Discovery through Advanced Computing) program led by Xianzhu Tang of the Los Alamos National Laboratory but with separate grants to each institution. I was the PI for Columbia University and the only person at Columbia directly funded by this SciDAC. Disruptions are a sudden loss of confinement in tokamaks, and a reliable method of preventing disruptions must be developed before tokamak fusion power plants become feasible. A related plasma confinement concept, the stellarator, is the only way known way of preventing disruptions with the required reliability. The largest devices, both existing and under construction, for confining plasmas for fusion using magnetic fields are tokamaks, so it is important to solve their disruption issues. The sudden loss of confinement in tokamaks can be from a bit of material falling into the plasma, which causes the plasma energy to be quickly lost by radiation, or by an instability causing a breakup of the confining surfaces formed by the magnetic field. This breakup can occur more than a million times faster than one would naively think possible. The sudden breakup of surfaces is called a fast magnetic reconnection and also results in a sudden cooling of the plasma.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2021

Secure LoRa Firmware Update with Adaptive Data Rate Techniques

Internet of Things (IoT) devices rely upon remote firmware updates to fix bugs, update embedded algorithms, and make security enhancements. Remote firmware updates are a significant burden to wireless IoT devices that operate using low-power wide-area network (LPWAN) technologies due to slow data rates. One LPWAN technology, Long Range (LoRa), has the ability to increase the data rate at the expense of range and noise immunity. The optimization of communications for maximum speed is known as adaptive data rate (ADR) techniques, which can be applied to accelerate the firmware update process for any LoRa-enabled IoT device. In this paper, we investigate ADR techniques in an application that provides remote monitoring of cattle using small, battery-powered devices that transmit data on cattle location and health using LoRa. In addition to issues related to firmware update speed, there are significant concerns regarding reliability and security when updating firmware on mobile, energy-constrained devices. A malicious actor could attempt to steal the firmware to gain access to embedded algorithms or enable faulty behavior by injecting their own code into the device. A firmware update could be subverted due to cattle moving out of the LPWAN range or the device battery not being sufficiently charged to complete the update process. To address these concerns, we propose a secure and reliable firmware update process using ADR techniques that is applicable to any mobile or energy-constrained LoRa device. The proposed system is simulated and then implemented to evaluate its performance and security properties.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2022

Semiconductor: Supply Chain Deep Dive Assessment

In February 2021, President Biden signed Executive Order (EO) 14017, “America’s Supply Chains,” directing seven executive agencies to evaluate the resilience and security of the nation’s critical supply chains and to craft strategies for six industrial bases that underpin America’s economic and national security. See Sec. 3(b) of E.O. 14017. As part of the one-year response to EO 14017, the U.S. Department of Energy (DOE), through the national laboratories, conducted evaluations of the supply chains that encompass the Energy Sector Industrial Base, with a particular focus on technologies required to decarbonize the U.S. by 2050. This report focuses on one of these technologies, semiconductors, both conventional and wide bandgap (WBG) power electronics (PE). As noted in the 100-Day report, conventional semiconductors are a keystone technology that are essential for the operation of nearly every electronic device, including those that are critical to decarbonization, such as electric vehicles (EVs), industrial and building applications, and electricity generation and end use. In addition, power electronics have been applied to industrial equipment to improve energy efficiency and enhance controllability. Power electronics have also been used to improve the reliability of data centers and critical infrastructure, including the stabilization of the electric grid while subjected to disturbances. Increasingly, power electronics are being used to integrate renewable energy and battery storage systems, enabling new grid services and the development of microgrids. It is estimated that 30% of the electricity used in the U.S. passes through power electronic devices, and studies suggest that this number could reach 80% as power electronics are deployed in more markets. Nearly all forms of electrified transportation will depend on power electronics. Power electronic systems utilize high-capacity semiconductor devices at their core. The continued growth in power electronics depends on sustained innovation in the semiconductor industry.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2024

Heterogeneous Integration Technologies for High-temperature, High-density, Low-profile Power Modules of Wide Bandgap Devices in Electric Drive Applications (Final Technical Report)

The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗