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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into “Beyond CMOS” and “More than Moore” paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. Finally, the outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Science challenges and research opportunities for plasma applications in microelectronics

Low-temperature plasmas (LTPs) are essential to manufacturing devices in the semiconductor industry, from creating extreme ultraviolet photons used in the most advanced lithography to thin film etching, deposition, and surface modifications. It is estimated that 40%–45% of all process steps needed to manufacture semiconductor devices use LTPs in one form or another. LTPs have been an enabling technology in the multidecade progression of the shrinking of device dimensions, often referred to as Moore’s law. New challenges in circuit and device design, novel materials, and increasing demands to achieve environmentally benign processing technologies require advances in plasma technology beyond the current state-of-the-art. The Department of Energy Office of Science Fusion Energy Sciences held a workshop titled Plasma Science for Microelectronics Nanofabrication in August 2022 to discuss the plasma science challenges and technical barriers that need to be overcome to continue to develop the innovative plasma technologies required to support and advance the semiconductor industry. One of the key outcomes of the workshop was identifying a set of priority research opportunities (PROs) to focus attention on the most strategic plasma science challenges to address to benefit the semiconductor industry. For each PRO, scientific challenges and recommended strategies to address those challenges were identified. Furthermore, this article summarizes the PROs identified by the workshop participants.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Cu-Cu direct bonding achieved by surface method at room temperature

The metal bonding is a key technology in the processes for the microelectromechanical systems (MEMS) devices and the semiconductor devices to improve functionality and higher density integration. Strong adhesion between surfaces at the atomic level is crucial; however, it is difficult to achieve close bonding in such a system. Cu films were deposited on Si substrates by vacuum deposition, and then, two Cu films were bonded directly by means of surface activated bonding (SAB) at room temperature. The two Cu films, with the surface roughness Ra about 1.3nm, were bonded by using SAB at room temperature, however, the bonding strength was very weak in this method. In order to improve the bonding strength between the Cu films, samples were annealed at low temperatures, between 323 and 473 K, in air. As the result, the Cu-Cu bonding strength was 10 times higher than that of the original samples without annealing.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2013

Exploring Graphene Field Effect Transistor Devices to Improve Spectral Resolution of Semiconductor Radiation Detectors

Graphene, a planar, atomically thin form of carbon, has unique electrical and material properties that could enable new high performance semiconductor devices. Graphene could be of specific interest in the development of room-temperature, high-resolution semiconductor radiation spectrometers. Incorporating graphene into a field-effect transistor architecture could provide an extremely high sensitivity readout mechanism for sensing charge carriers in a semiconductor detector, thus enabling the fabrication of a sensitive radiation sensor. In addition, the field effect transistor architecture allows us to sense only a single charge carrier type, such as electrons. This is an advantage for room-temperature semiconductor radiation detectors, which often suffer from significant hole trapping. Here we report on initial efforts towards device fabrication and proof-of-concept testing. This work investigates the use of graphene transferred onto silicon and silicon carbide, and the response of these fabricated graphene field effect transistor devices to stimuli such as light and alpha radiation.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
DOE OSTI2018

Development of a Physical-Topological Model for the Response of a High-Power Vertical DMOS Transistor to the Effect of Pulsed Gamma-Radiation

A method for developing models of semiconductor devices with two-dimensional nonuniform concentration profiles of donors and acceptors in working regions of a semiconductor device structure is for the first time proposed based on a complex of physical-topological modeling of charge carrier transport and process simulation of the forming processes of the device structure. The application of process simulation is due to the need to correctly define the parameters of the semiconductor device structure, which are used as initial data to calculate the electron transport according to the physical-topological model. The parameters of production processes of ion implantation, diffusion, and lithography, which were refined during process simulation, are determined for a high-power metal—oxide—semiconductor (MOS) transistor forming by the double diffusion method in accordance with known electrical characteristics and measured geometrical sizes of the structure. This results in two-dimensional distribution profiles of donors and acceptors in p–n junctions necessary to calculate the transistor breakdown under the effect of pulsed γ radiation. Breakdown processes are modeled with the help of the physical-topological model based on the Poisson and continuity equations as well as expressions for the diffusion and drift current densities in the transistor. Accounting for carriers formed at the instant of γ irradiation is implemented by the introduction of the dependence of the generation coefficient of electron–hole pairs on the radiation-dose power. The results of calculations correlate well with the experimental data, which makes it possible to give a conclusion regarding the adequacy of the proposed complex model.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Low-energy electro- and photo-emission spectroscopy of GaN materials and devices

In hot-electron semiconductor devices, carrier transport extends over a wide range of conduction states, which often includes multiple satellite valleys. Electrical measurements can hardly give access to the transport processes over such a wide range without resorting to models and simulations. An alternative experimental approach however exists which is based on low-energy electron spectroscopy and provides, in a number of cases, very direct and selective information on hot-electron transport mechanisms. Recent results obtained in GaN crystals and devices by electron emission spectroscopy are discussed. Using near-band-gap photoemission, the energy position of the first satellite valley in wurtzite GaN is directly determined. By electro-emission spectroscopy, we show that the measurement of the electron spectrum emitted from a GaN p-n junction and InGaN/GaN light-emitting diodes (LEDs) under electrical injection of carriers provides a direct observation of transport processes in these devices. In particular, at high injected current density, high-energy features appear in the electro-emission spectrum of the LEDs showing that Auger electrons are being generated in the active region. These measurements allow us identifying the microscopic mechanism responsible for droop which represents a major hurdle for widespread adoption of solid-state lighting.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Energy storage device with large charge separation

High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach. The first aspect is to provide high density energy storage in semiconductor devices based on formation of a plasma in the semiconductor. The second aspect is to provide high density energy storage based on charge separation in a p-n junction.

25 ENERGY STORAGE↗
DOE OSTI2018

Energy storage device with large charge separation

High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach. The first aspect is to provide high density energy storage in semiconductor devices based on formation of a plasma in the semiconductor. The second aspect is to provide high density energy storage based on charge separation in a p-n junction.

25 ENERGY STORAGE↗
DOE OSTI2021

Optical coupler for heterogeneous integration

In an optical apparatus, an introduced semiconductor device is heterointegrated on a silicon-based platform containing a silicon-based waveguide. A polymeric waveguide is optically coupled to the introduced semiconductor device and overlies at least a portion of the silicon-based waveguide. The polymeric waveguide is conformed as a multimode interference (MMI) coupler between the introduced semiconductor device and the silicon-based waveguide. At least the polymeric waveguide, and in embodiments, also the silicon-based waveguide, is tapered with a shape that effectuates optical coupling to the silicon-based waveguide.

Gehl, Michael↗
DOE OSTI2019

Gas Ingress and Egress of MEMS Multi-Chip Modules and MEMS Devices

Hermetic microcircuit packaging was the dominant method of protecting semiconductor devices in the 1960s and 1970s. After losing majority market sectors to plastic encapsulated microelectronics over the last a few decades, hermetic packaging remains the preferred method of protecting semiconductor devices for critical applications such as in military, space, and medical fields, where components and systems are required to serve for several decades. MEMS devices impose additional challenges to packaging by requiring specific internal cavity pressures to function properly or deliver the needed quality (Q) factors. In MEMS multichip modules, internal pressure requirement conflicts arise when different MEMS devices require different internal gases and pressures. The authors developed a closed-formed equation to model pressure changes of hermetic enclosures due to gas ingression. This article expands the authors mathematical model to calculate gas pressure of a MEMS multichip module package as well as those of MEMS devices inside the multichip module package. These equations are not only capable of calculating service lifetimes of MEMS devices and multi-chip modules but can also help develop MEMS device packaging strategies to extend the service life of MEMS multi-chip modules.

36 MATERIALS SCIENCE↗
DOE OSTI2021

A perspective on the electro-thermal co-design of ultra-wide bandgap lateral devices

Fundamental research and development of ultra-wide bandgap (UWBG) semiconductor devices are under way to realize next-generation power conversion and wireless communication systems. Devices based on aluminum gallium nitride (AlxGa1-xN, x is the Al composition), ..beta..-phase gallium oxide (..beta..-Ga2O3), and diamond give promise to the development of power switching devices and radio frequency power amplifiers with higher performance and efficiency than commercial wide bandgap semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC). However, one of the most critical challenges for the successful deployment of UWBG device technologies is to overcome adverse thermal effects that impact the device performance and reliability. Overheating of UWBG devices originates from the projected high power density operation and poor intrinsic thermal properties of AlxGa1-xN and ..beta..-Ga2O3. This Perspective delineates the need and process for the "electro-thermal co-design" of laterally configured UWBG electronic devices and provides a comprehensive review of current state-of-the-art thermal characterization methods, device thermal modeling practices, and both device- and package-level thermal management solutions.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Band-Gap Engineering at a Semiconductor-Crystalline Oxide Interface

The epitaxial growth of crystalline oxides on semiconductors provides a pathway to introduce new functionalities to semiconductor devices. Key to electrically coupling crystalline oxides with semiconductors to realize functional behavior is controlling the manner in which their bands align at interfaces. Here we apply principles of band gap engineering traditionally used at heterojunctions between conventional semiconductors to control the band offset between a single crystalline oxide and a semiconductor. Reactive molecular beam epitaxy is used to realize atomically abrupt and structurally coherent interfaces between SrZr x Ti 1-x O 3 and Ge, in which the band gap of the former is enhanced with Zr content x. We present structural, electrical and photoemission characterization of SrZr x Ti 1-x O 3 3-Ge heterojunctions for x = 0.2 to 0.75 and demonstrate the band offset can be tuned from type-II to type-I. The type-I band offset provides a platform to integrate the dielectric, ferroelectric and ferromagnetic functionalities of oxides with semiconducting devices.

42 ENGINEERING↗
DOE OSTI2016

Polymerization of defect states at dislocation cores in InAs

Dislocations are essentially lines of point defects which can act as recombination centers in semiconductor devices. These point defects do not behave as isolated defects. Their spatial proximity enables them to hybridize into a one-dimensional band, and the distribution of resulting defect-band states is determined by both the position of the band and its dispersion. In the case of glissile 90° partial dislocations in III-V semiconductors, the dislocation core can adopt a variety of different reconstructions. Each of these reconstructions has a different arrangement of point defects, which affects the hybridization into defect bands and their associated dispersion. Here, we illustrate these principles by performing first-principles calculations for InAs and find that some defect levels for InAs dislocations lie outside of the band gap where they cannot act as recombination centers. To provide some insight into the electronic structure of dislocations in ternary alloys, some examples relevant to InGaAs and GaAsP are included.

36 MATERIALS SCIENCE↗
DOE OSTI2016

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As the result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2018

Development and Validation of a SiC Based 50 kW Grid-Connected PV Inverter: Preprint

In this digest a 50kW string PV inverter formed using all SiC semiconductor devices is presented. The inverter design includes additively manufactured power block, symmetrical Y-core inductors for ac side filter, and advanced inverter functionality for grid support. This inverter utilizes the conventional three-phase Voltage Source Inverter topology and optimizes the design for SiC based devices. This paper presents the full functional validation of the designed inverter along with quantification of the efficiency and power density. The performance of the inverter for high dc-bus voltage without multi-level topology to exploit SiC advantages is also presented in this digest. The full paper will include details of inverter design, optimization and further experimental validation.

14 SOLAR ENERGY↗