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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

Random Dopant Threshold Voltage Fluctuations in 50 nm Epitaxial Channel MOSFETs: A 3D 'Atomoc' Simulation Study

3D 'atomistic' simulations are used to study random dopant related threshold voltage fluctuations in 50 nm MOSFETs. Comparisons are made between conventionally doped transistors and transistors with thin epitaxial silicon layers on heavily doped silicon. Issues related to both the optimum threshold voltage control and the suppression of the threshold voltage dispersion are addressed.

Asenov, Asen↗
NASA NTRS2003

High-Sensitivity X-ray Polarimetry with Amorphous Silicon Active-Matrix Pixel Proportional Counters

Photoelectric X-ray polarimeters based on pixel micropattern gas detectors (MPGDs) offer order-of-magnitude improvement in sensitivity over more traditional techniques based on X-ray scattering. This new technique places some of the most interesting astronomical observations within reach of even a small, dedicated mission. The most sensitive instrument would be a photoelectric polarimeter at the focus of 2 a very large mirror, such as the planned XEUS. Our efforts are focused on a smaller pathfinder mission, which would achieve its greatest sensitivity with large-area, low-background, collimated polarimeters. We have recently demonstrated a MPGD polarimeter using amorphous silicon thin-film transistor (TFT) readout suitable for the focal plane of an X-ray telescope. All the technologies used in the demonstration polarimeter are scalable to the areas required for a high-sensitivity collimated polarimeter. Leywords: X-ray polarimetry, particle tracking, proportional counter, GEM, pixel readout

Black, J. K.↗
NASA NTRS2015

New Insights on Subsurface Imaging of Carbon Nanotubes in Polymer Composites via Scanning Electron Microscopy

Despite many studies of subsurface imaging of carbon nanotube (CNT)-polymer composites via scanning electron microscopy (SEM), significant controversy exists concerning the imaging depth and contrast mechanisms. We studied CNT-polyimide composites and, by threedimensional reconstructions of captured stereo-pair images, determined that the maximum SEM imaging depth was typically hundreds of nanometers. The contrast mechanisms were investigated over a broad range of beam accelerating voltages from 0.3 to 30 kV, and ascribed to modulation by embedded CNTs of the effective secondary electron (SE) emission yield at the polymer surface. This modulation of the SE yield is due to non-uniform surface potential distribution resulting from current flows due to leakage and electron beam induced current. The importance of an external electric field on SEM subsurface imaging was also demonstrated. The insights gained from this study can be generally applied to SEM nondestructive subsurface imaging of conducting nanostructures embedded in dielectric matrices such as graphene-polymer composites, silicon-based single electron transistors, high resolution SEM overlay metrology or e-beam lithography, and have significant implications in nanotechnology.

Zhao, Minhua↗
NASA NTRS2000

Temperature Distribution Within a Defect-Free Silicon Carbide Diode Predicted by a Computational Model

Most solid-state electronic devices diodes, transistors, and integrated circuits are based on silicon. Although this material works well for many applications, its properties limit its ability to function under extreme high-temperature or high-power operating conditions. Silicon carbide (SiC), with its desirable physical properties, could someday replace silicon for these types of applications. A major roadblock to realizing this potential is the quality of SiC material that can currently be produced. Semiconductors require very uniform, high-quality material, and commercially available SiC tends to suffer from defects in the crystalline structure that have largely been eliminated in silicon. In some power circuits, these defects can focus energy into an extremely small area, leading to overheating that can damage the device. In an effort to better understand the way that these defects affect the electrical performance and reliability of an SiC device in a power circuit, the NASA Glenn Research Center at Lewis Field began an in-house three-dimensional computational modeling effort. The goal is to predict the temperature distributions within a SiC diode structure subjected to the various transient overvoltage breakdown stresses that occur in power management circuits. A commercial computational fluid dynamics computer program (FLUENT-Fluent, Inc., Lebanon, New Hampshire) was used to build a model of a defect-free SiC diode and generate a computational mesh. A typical breakdown power density was applied over 0.5 msec in a heated layer at the junction between the p-type SiC and n-type SiC, and the temperature distribution throughout the diode was then calculated. The peak temperature extracted from the computational model agreed well (within 6 percent) with previous first-order calculations of the maximum expected temperature at the end of the breakdown pulse. This level of agreement is excellent for a model of this type and indicates that three-dimensional computational modeling can provide useful predictions for this class of problem. The model is now being extended to include the effects of crystal defects. The model will provide unique insights into how high the temperature rises in the vicinity of the defects in a diode at various power densities and pulse durations. This information also will help researchers in understanding and designing SiC devices for safe and reliable operation in high-power circuits.

Kuczmarski, Maria A.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2002

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Pain, Bedabrata↗
NASA NTRS2005

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Zheng, Xinyu↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS1972

Solid state image sensing arrays

The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.

Sadasiv, G.↗
NASA NTRS1980

The GSFC Mark-2 three band hand-held radiometer

A self-contained, portable, hand-radiometer designed for field usage was constructed and tested. The device, consisting of a hand-held probe containing three sensors and a strap supported electronic module, weighs 4 1/2 kilograms. It is powered by flashlight and transistor radio batteries, utilizes two silicon and one lead sulfide detectors, has three liquid crystal displays, sample and hold radiometric sampling, and its spectral configuration corresponds to LANDSAT-D's thematic mapper bands. The device was designed to support thematic mapper ground-truth data collection efforts and to facilitate 'in situ' ground-based remote sensing studies of natural materials. Prototype instruments were extensively tested under laboratory and field conditions with excellent results.

Tucker, C. J.↗
NASA NTRS2003

Power Electronics Being Developed for Deep Space Cryogenic Applications

Electronic circuits and systems designed for deep space missions need to operate reliably and efficiently in harsh environments that include very low temperatures. Spacecraft that operate in such cold environments carry a large number of heaters so that the ambient temperature for the onboard electronics remains near 20 C. Electronics that can operate at cryogenic temperatures will simplify system design and reduce system size and weight by eliminating the heaters and their associated structures. As a result, system development and launch cost will be reduced. At the NASA Glenn Research Center, an ongoing program is focusing on the development of power electronics geared for deep space low-temperature environments. The research and development efforts include electrical components design, circuit design and construction, and system integration and demonstration at cryogenic temperatures. Investigations are being carried out on circuits and systems that are targeted for use in NASA missions where low temperatures will be encountered: devices such as ceramic and tantalum capacitors, metal film resistors, semiconductor switches, magnetics, and integrated circuits including dc/dc converters, operational amplifiers, voltage references, and motor controllers. Test activities cover a wide range of device and circuit performance under simple as well as complex test conditions, such as multistress and thermal cycling. The effect of low-temperature conditions on the switching characteristics of an advanced silicon-on-insulator field effect transistor is shown. For gate voltages (VGS) below 2.6 V, drain currents at -190 C are lower than drain currents at room temperature (20 C).

Patterson, Richard L.↗
NASA NTRS2015

CarbAl Heat Transfer Material

The increasing use of power electronics, such as high-current semiconductor devices and modules, within space vehicles is driving the need to develop specialty thermal management materials in both the packaging of these discrete devices and the packaging of modules consisting of these device arrays. Developed by Applied Nanotech, Inc. (ANI), CarbAl heat transfer material is uniquely characterized by its low density, high thermal diffusivity, and high thermal conductivity. Its coefficient of thermal expansion (CTE) is similar to most power electronic materials, making it an effective base plate substrate for state-of-the-art silicon carbide (SiC) super junction transistors. The material currently is being used to optimize hybrid vehicle inverter packaging. Adapting CarbAl-based substrates to space applications was a major focus of the SBIR project work. In Phase I, ANI completed modeling and experimentation to validate its deployment in a space environment. Key parameters related to cryogenic temperature scaling of CTE, thermal conductivity, and mechanical strength. In Phase II, the company concentrated on improving heat sinks and thermally conductive circuit boards for power electronic applications.

Fink, Richard↗