Analytic techniques for evaluating software designs and methodologies
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Development of tools that include the STP theorem poer and its associated Design Verification Systems; PHIL, a meta-programmable context sensitive structured editor; Pegasus, a system for support of graphical programming; and OBJ, an ultra high level programming language based on rewrite rules and abstract data type is reported.
The capability of programmers and non-programmers to specify problem solutions by developing example-solutions and also for the programmers by writing computer programs was investigated; each method of specification was accomplished at various levels of problem complexity. The level of difficulty of each problem was reflected by the number of steps needed by the user to develop a solution. Machine processing of the user inputs permitted inferences to be developed about the algorithms required to solve a particular problem. The interactive feedback of processing results led users to a more precise definition of the desired solution. Two participant groups (programmers and bookkeepers/accountants) working with three levels of problem complexity and three levels of processor complexity were used. The experimental task employed required specification of a logic for solution of a Navy task force problem.
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The comparative computational efficiencies of the finite element (FEM), boundary element (BEM), and hybrid boundary element-finite element (HVFEM) analysis techniques are evaluated for representative bounded domain interior and unbounded domain exterior problems in elastostatics. Computational efficiency is carefully defined in this study as the computer time required to attain a specified level of solution accuracy. The study found the FEM superior to the BEM for the interior problem, while the reverse was true for the exterior problem. The hybrid analysis technique was found to be comparable or superior to both the FEM and BEM for both the interior and exterior problems.
The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.
Design techniques which may be applied to make program testing easier were investigated. Methods for modifying a program to generate additional data which we refer to as a certification trail are presented. This additional data is designed to allow the program output to be checked more quickly and effectively. Certification trails were described primarily from a theoretical perspective. A comprehensive attempt to assess experimentally the performance and overall value of the certification trail method is reported. The method was applied to nine fundamental, well-known algorithms for the following problems: convex hull, sorting, huffman tree, shortest path, closest pair, line segment intersection, longest increasing subsequence, skyline, and voronoi diagram. Run-time performance data for each of these problems is given, and selected problems are described in more detail. Our results indicate that there are many cases in which certification trails allow for significantly faster overall program execution time than a 2-version programming approach, and also give further evidence of the breadth of applicability of this method.
The goal of this project was the feasibility study of a particular architecture of a digital signal processing machine operating in real time which could do in a pipeline fashion the computation of the fast Fourier transform (FFT) of a time-domain sampled complex digital data stream. The particular architecture makes use of simple identical processors (called inner product processors) in a linear organization called a systolic array. Through computer simulation the new architecture to compute the FFT with systolic arrays was proved to be viable, and computed the FFT correctly and with the predicted particulars of operation. Integrated circuits to compute the operations expected of the vital node of the systolic architecture were proven feasible, and even with a 2 micron VLSI technology can execute the required operations in the required time. Actual construction of the integrated circuits was successful in one variant (fixed point) and unsuccessful in the other (floating point).
Detailed results of this three-year project are available in 37 publications, including 7 book chapters, 3 journal articles, and 27 refereed conference proceedings. In addition, various aspects of the project were the subject of 31 invited presentations and 6 tutorials at international conferences and workshops. Good descriptions of prior and ongoing work on foundational technologies in Brahms, KAoS, NOMADS, and the PSA project can be found in numerous publications not listed here.
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A typical Beowulf system, such as the machine at the Jet Propulsion Laboratory (JPL), may comprise 16 nodes interconnected by 100 base T Fast Ethernet. Each node may include a single Inter Pentium Pro 200 MHz microprocessor, 128 MBytes of DRAM, 2.5 GBytes of IDE disk, and PCI bus backplane, and an assortment of other devices.
In this survey paper, we bring together current progress to date in identifying design patterns for use with the real-time specification for Java in a format consistent with contemporary patterns descriptions.
NASA's new direction is towards.
The viewgraph presentation provides an introduction to the James Webb Space Telescope (JWST). The first part provides a brief overview of Matlab toolkits including CodeV, OSLO, and Zemax Toolkits. The toolkit overview examines purpose, layout, how Matlab gets data from CodeV, function layout, and using cvHELP. The second part provides examples of use with JWST, including wavefront sensitivities and alignment simulations.
This report describes the development of the system identification (SysID) rack custom application code. This code is used to automate the system identification experimental processes for the National Aeronautics and Space Administration (NASA) Combined Cycle Engine Large-Scale Inlet for Mode Transition Experiments testbed. This series of experiments took place in the NASA Glenn Research Center (GRC) 10 foot by 10 foot (10x10) Supersonic Wind Tunnel (SWT) test facility. The SysID code was developed to apply command signals to testbed actuators, receive actuator feedback signals, and acquire sensor data which is used to identify the dynamics of the experimental processes. This code development and the process identification experiments were conducted during Phase-2 testing at various operating points. These points were predefined from data collected during the Phase-1 testbed characterization experiments. The developed SysID code was executed on a NASA designed and built real-time data acquisition (DAQ) and controls (SysID) rack. This report focuses on the development of the SysID rack real-time DAQ and control hardware and the custom application code used to automate the system identification process. The implementation of this reliable and efficient data acquisition and controls development tool is demonstrated by presenting an example of experimental data collected to be used for system identification.
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Slide presentation detailing the Vertiport Automation System system design review