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At least 127 records · Page 7

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NASA NTRS2002

Commercial-Off-The-Shelf Microelectromechanical Systems (MEMS) Flow-Measurement Probes Fabricated And Assembled

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at the NASA Glenn Research Center have been fabricating packaging components and assembling a set of unique probes using commercial-off-the-shelf microelectromechanical systems (MEMS) integrated circuits (computer chips). Using MEMS as an alternative has some compelling advantages over standard measurement devices. Sensor technologies have matured through high-production usage in industries such as automotive and aircraft manufacturers. Currently, MEMS are the choice in applications such as tire pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Conventional instrumentation uses tubing buried in the model aerodynamic surfaces or wind tunnel walls. The measurements are made when pressure is introduced at the tube opening. The pressure then must travel the tubing for lengths ranging from 20 to hundreds of feet before reaching an electronic signal conditioner. This condition causes a considerable amount of damping and requires measurements to be made only after the test rig has reached steady-state operation. The electronic MEMS pressure sensor is able to take readings continuously under dynamic states in nearly real time. The use of stainless steel tubing for pressure measurements requires many tubes to be cleaned, cut to length, carefully installed, and delicately deburred and spliced for use. A cluster of a few hundred 1/16-in.- (0.0625-in.-) diameter tubes (not uncommon in research testing facilities) can be several inches in diameter and may weigh enough to require two men to handle. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of the 1/16-in. tubing with room to spare. The P592 piezoresistive silicon pressure sensor (Lucas NovaSensor, Fremont, CA) was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The chip is 1 mm square by 0.6 mm thick (0.039 by 0.023 in.) with 0.12-mm (0.005-in.) wire connection tabs. Three MEMS chips were used to build the first type of flow-angularity probe. This MEMS probe will be demonstrated as an alternative to a standard tube type "Cobra Probe" now used routinely in wind tunnel and aeronautical hardware applications. The response time and accuracy would allow the probe to be translated on an actuator across a flow field, yielding precision dynamic measurements not possible with conventional instrumentation. The low profile, the minimal power requirement, the rugged construction, and the moderate cost all contribute to making MEMS sensors the enticing choice instrument in future research measurement needs. The MEMS probe efforts are a continuation of work initiated by Brian Willis, without whose foresight and efforts this project would never have been realized. This task was funded through cooperation with the NASA Electronic Parts and Packaging (NEPP) program at the Jet Propulsion Laboratory.

Redding, Chip↗

NASA NTRS2004

COTS MEMS Flow-Measurement Probes

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at Glenn Research Center have been fabricating packaging components and assembling a set of unique probes that contain commercial off-the-shelf (COTS) microelectromechanical systems (MEMS) sensor chips. MEMS sensor chips offer some compelling advantages over standard macroscopic measurement devices. MEMS sensor technology has matured through mass production and use in the automotive and aircraft industries. At present, MEMS are the devices of choice for sensors in such applications as tire-pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Compactness, minimality of power demand, rugged construction, and moderate cost all contribute to making MEMS sensors attractive for instrumentation for future research. Conventional macroscopic flow-measurement instrumentation includes tubes buried beneath the aerodynamic surfaces of wind-tunnel models or in wind-tunnel walls. Pressure is introduced at the opening of each such tube. The pressure must then travel along the tube before reaching a transducer that generates an electronic signal. The lengths of such tubes typically range from 20 ft (approx.= 6 m) to hundreds of feet (of the order of 100 m). The propagation of pressure signals in the tubes damps the signals considerably and makes it necessary to delay measurements until after test rigs have reached steady-state operation. In contrast, a MEMS pressure sensor that generates electronic output can take readings continuously under dynamic conditions in nearly real time. In order to use stainless-steel tubing for pressure measurements, it is necessary to clean many tubes, cut them to length, carefully install them, delicately deburr them, and splice them. A cluster of a few hundred 1/16-in.- (approx.=1.6-mm-) diameter tubes (such clusters are common in research testing facilities) can be several inches (of the order of 10 cm) in diameter and could weigh enough that two technicians are needed to handle it. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of a 1/16-in. tube with room to spare. The Lucas NovaSensor P592 piezoresistive silicon pressure sensor was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The sensor chip is 1 mm square by 0.6 mm thick (about 0.039 by 0.039 by 0.024 in.) and includes 0.12-mm (approx.=0.005-in.) wire connection tabs. The figure shows a flow-angularity probe that was built by use of three such MEMS chips. It is planned to demonstrate this MEMS probe as an alternative to a standard tube-type "Cobra" probe now used routinely in wind tunnels and aeronautical hardware. This MEMS probe could be translated across a flow field by use of a suitable actuator, so that its accuracy and the shortness of its response time could be exploited to obtain precise dynamic measurements of a sort that cannot be made by use of conventional tubing-based instrumentation.

Redding, Chip↗

NASA NTRS2003

High-Performance Solid-State W-Band Power Amplifiers

The figure shows one of four solid-state power amplifiers, each capable of generating an output power greater than or equal to 240 mW over one of four overlapping frequency bands from 71 to 106 GHz. (The bands are 71 to 84, 80 to 92, 88 to 99, and 89 to 106 GHz.) The amplifiers are designed for optimum performance at a temperature of 130 K. These amplifiers were developed specifically for incorporation into frequency-multiplier chains in local oscillators in a low-noise, far-infrared receiving instrument to be launched into outer space to make astrophysical observations. The designs of these amplifiers may also be of interest to designers and manufacturers of terrestrial W-band communication and radar systems. Each amplifier includes a set of six high-electron-mobility transistor (HEMT) GaAs monolithic microwave integrated-circuit (MMIC) chips, microstrip cavities, and other components packaged in a housing made from A-40 silicon-aluminum alloy. This alloy was chosen because, for the original intended spacecraft application, it offers an acceptable compromise among the partially competing requirements for high thermal conductivity, low mass, and low thermal expansion. Problems that were solved in designing the amplifiers included designing connectors and packages to fit the available space; designing microstrip signal-power splitters and combiners; matching of impedances across the frequency bands; matching of the electrical characteristics of those chips installed in parallel power-combining arms; control and levelling of output power across the bands; and designing the MMICs, microstrips, and microstrip cavities to suppress tendencies toward oscillation in several modes, both inside and outside the desired frequency bands.

Gaier, Todd↗

NASA NTRSDate not supplied

Open-source Wireless Sensor Network (Wi-Se Net) for Flexible Deployment

Wireless sensors, especially if battery powered, have a number of advantages over wired sensors for flexible or temporary diagnostic deployment in a field or lab setting. Recent advances in wireless technology and microprocessor boards have produced a variety of inexpensive off-the shelf chips which can communicate wirelessly with simple protocols. This paper describes the design and implementation of a highly customizable wireless sensor network (called WiSe Net) using inexpensive open-source hardware components as wireless nodes. These wireless sensor nodes can transmit data at a rate <250 Hz, can be battery powered, and have a small footprint (2x5 cm). In addition, a preliminary over-the-air programming system was developed to allow for simple wireless configuration when active. The network performance was demonstrated by taking distributed and electrically isolated temperature measurements on a high-voltage lab apparatus. Although this test case is in a laboratory setting, this network architecture could be easily repurposed for various other forms of monitoring

Wireless Sensor Network↗

NASA NTRSDate not supplied

Open-source Wireless Sensor Network (Wi-Se Net) for Flexible Deployment

Wireless Sensor Network↗

NASA NTRSDate not supplied

Open-source Wireless Sensor Network (Wi-Se Net) for Flexible Deployment

Wireless sensors, especially if battery powered, have a number of advantages over wired sensors for flexible or temporary diagnostic deployment in a field or lab setting. Recent advances in wireless technology and microprocessor boards have produced a variety of inexpensive off-the shelf chips which can communicate wirelessly with simple protocols. This paper describes the design and implementation of a highly customizable wireless sensor network (called Wi-Se Net) using inexpensive open-source hardware components as wireless nodes. These wireless sensor nodes can transmit data at a rate <250 Hz, can be battery powered, and have a small footprint (2x5 cm). In addition, a preliminary over-the-air programming system was developed to allow for simple wireless configuration when active. The network performance was demonstrated by taking distributed and electrically isolated temperature measurements on a high-voltage lab apparatus. Although this test case is in a laboratory setting, this network architecture could be easily repurposed for various other forms of monitoring.

Wireless Sensor Network↗

DOE OSTI2022

Astronauts Plasma-Derived Exosomes Induced Aberrant EZH2-Mediated H3K27me3 Epigenetic Regulation of the Vitamin D Receptor

There are unique stressors in the spaceflight environment. Exposure to such stressors may be associated with adverse effects on astronauts' health, including increased cancer and cardiovascular disease risks. Small extracellular vesicles (sEVs, i.e., exosomes) play a vital role in intercellular communication and regulate various biological processes contributing to their role in disease pathogenesis. To assess whether spaceflight alters sEVs transcriptome profile, sEVs were isolated from the blood plasma of 3 astronauts at two different time points: 10 days before launch (L-10) and 3 days after return (R+3) from the Shuttle mission. AC16 cells (human cardiomyocyte cell line) were treated with L-10 and R+3 astronauts-derived exosomes for 24 h. Total RNA was isolated and analyzed for gene expression profiling using Affymetrix microarrays. Enrichment analysis was performed using Enrichr. Furthermore, transcription factor (TF) enrichment analysis using the ENCODE/ChEA Consensus TF database identified gene sets related to the polycomb repressive complex 2 (PRC2) and Vitamin D receptor (VDR) in AC16 cells treated with R+3 compared to cells treated with L-10 astronauts-derived exosomes. Further analysis of the histone modifications using datasets from the Roadmap Epigenomics Project confirmed enrichment in gene sets related to the H3K27me3 repressive mark. Interestingly, analysis of previously published H3K27me3–chromatin immunoprecipitation sequencing (ChIP-Seq) ENCODE datasets showed enrichment of H3K27me3 in the VDR promoter. Collectively, our results suggest that astronaut-derived sEVs may epigenetically repress the expression of the VDR in human adult cardiomyocytes by promoting the activation of the PRC2 complex and H3K27me3 levels.

59 BASIC BIOLOGICAL SCIENCES↗

NASA NTRS2003

Integrated Electrode Arrays for Neuro-Prosthetic Implants

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Brandon, Erik↗

DOE OSTI2021

Understanding HPC Benchmark Performance on Intel Broadwell and Cascade Lake Processors

Hardware platforms in high performance computing are constantly getting more complex to handle even when considering multicore CPUs alone. Numerous features and configuration options in the hardware and the software environment that are relevant for performance are not even known to most application users or developers. Microbenchmarks, i.e., simple codes that fathom a particular aspect of the hardware, can help to shed light on such issues, but only if they are well understood and if the results can be reconciled with known facts or performance models. The insight gained from microbenchmarks may then be applied to real applications for performance analysis or optimization. In this paper we investigate two modern Intel x86 server CPU architectures in depth: Broadwell EP and Cascade Lake SP. We highlight relevant hardware configuration settings that can have a decisive impact on code performance and show how to properly measure on-chip and off-chip data transfer bandwidths. The new victim L3 cache of Cascade Lake and its advanced replacement policy receive due attention. Finally we use DGEMM, sparse matrix-vector multiplication, and the HPCG benchmark to make a connection to relevant application scenarios.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1991

Report on the formal specification and partial verification of the VIPER microprocessor

The VIPER microprocessor chip is partitioned into four levels of abstractions. At the highest level, VIPER is described with decreasingly abstract sets of functions in LCF-LSM. At the lowest level are the gate-level models in proprietary CAD languages. The block-level and gate-level specifications are also given in the ELLA simulation language. Among VIPER's deficiencies are the fact that there is no notion of external events in the top-level specification, and it is impossible to use the top-level specifications to prove abstract properties of programs running on VIPER computers. There is no complete proof that the gate-level specifications implement the top-level specifications. Cohn's proof that the major-state machine correctly implements the top-level specifications has no formal connection with any of the other proof attempts. None of the latter address resetting the machine, memory timeout, forced error, or single step modes.

Brock, Bishop↗

NASA NTRS1992

Analysis of fault-tolerant neurocontrol architectures

The fault-tolerance of analog parallel distributed implementations of a multivariable aircraft neurocontroller is analyzed by simulating weight and neuron failures in a simplified scheme of analog processing based on the functional architecture of the ETANN chip (Electrically Trainable Artificial Neural Network). The neural information processing is found to be only partially distributed throughout the set of weights of the neurocontroller synthesized with the backpropagation algorithm. Although the degree of distribution of the neural processing, and consequently the fault-tolerance of the neurocontroller, could be enhanced using Locally Distributed Weight and Neuron Approaches, a satisfactory level of fault-tolerance could only be obtained by retraining the degrated VLSI neurocontroller. The possibility of maintaining neurocontrol performance and stability in the presence of single weight of neuron failures was demonstrated through an automated retraining procedure of the neurocontroller based on a pre-programmed choice and sequence of the training parameters.

Troudet, T.↗

NASA NTRS2018

GOES-16 ABI Navigation Assessment

The US Geostationary Operational Environmental Satellite â€“ R Series (GOES-R) was launched on November 19, 2016and was designated GOES-16 upon reaching geostationary orbit ten days later. After checkout and calibration, GOES-16 was relocated to its operational location of 75.2 degrees west and officially became GOES East on December 18, 2017. The Advanced Baseline Imager (ABI) is the primary instrument on the GOES-R series for imaging Earth's surface and atmosphere to significantly improve the detection and observation of severe environmental phenomena. A team supporting the GOES-R Flight Project at NASA's Goddard Space Flight Center developed algorithms and software for independent verification of ABI Image Navigation and Registration (INR), which became known as the INR Performance Assessment Tool Set (IPATS). In this paper, we will briefly describe IPATS on top concept level, and then introduce the Landsat chips, chip registration algorithms, and how IPATS measurements are filtered. We present GOES-16 navigation (NAV) errors from flight data from January 2017 to May 2018. The results show a) IPATS characterized INR variations throughout the post-launch test phase; and b) ABI INR has improved over time as post-launch tests were performed and corrections applied. Finally, we will describe how estimated NAV errors have been used to assess and understand satellite attitude anomalies and scale errors etc. This paper shows that IPATS is an effective tool for assessing and improving GOES-16 ABI INR and is also useful for INR long-term monitoring.

GOES-R↗

NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗

NASA NTRS2005

Medium power amplifiers covering 90 - 130 GHz for telescope local oscillators

This paper describes a set of power amplifier (PA) modules containing InP High Electron Mobility Transistor (HEMT) Monolithic Millimeter-wave Integrated Circuit (MMIC) chips. The chips were designed and optimized for local oscillator sources in the 90-130 GHz band for the Atacama Large Millimeter Array telescope. The modules feature 20-45 mW of output power, to date the highest power from solid state HEMT MMIC modules above 110 GHz.

coplanar waveguides↗

NASA NTRS2014

Scalable Background-Limited Polarization-Sensitive Detectors for mm-wave Applications

We report on the status and development of polarization-sensitive detectors for millimeter-wave applications. The detectors are fabricated on single-crystal silicon, which functions as a low-loss dielectric substrate for the microwave circuitry as well as the supporting membrane for the Transition-Edge Sensor (TES) bolometers. The orthomode transducer (OMT) is realized as a symmetric structure and on-chip filters are employed to define the detection bandwidth. A hybridized integrated enclosure reduces the high-frequency THz mode set that can couple to the TES bolometers. An implementation of the detector architecture at Q-band achieves 90% efficiency in each polarization. The design is scalable in both frequency coverage, 30-300 GHz, and in number of detectors with uniform characteristics. Hence, the detectors are desirable for ground-based or space-borne instruments that require large arrays of efficient background-limited cryogenic detectors.

Millimeter-Wave Detectors↗

DOE OSTI2023

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2024

AI-Enhanced Co-Design for Next-Generation Microelectronics: Innovating Innovation (Workshop Report)

The Artificial Intelligence Enhanced Co-Design for Next Generation Microelectronics virtual workshop was held April 4-5, 2023, and attended by subject matter experts from universities, industry, and national laboratories. This was the third in a series of workshops to motivate the research community to identify and address major challenges facing microelectronics research and production. The 2023 workshop focused on a set of topics from materials to computing algorithms, and included discussions on relevant federal legislation and such as the Creating Helpful Incentives to Produce Semiconductors and Science Act (CHIPS Act) which was signed into law in the summer of 2022. Talks at the workshop included edge computing in radiation environments, new materials for neuromorphic computing, advanced packaging for microelectronics, and new AI techniques. We also received project updates from several of the Department of Energy (DOE) microelectronics co-design projects funded in the fall of 2021, and from three of the Energy Frontier Research Centers (EFRCs) that had been funded in the fall of 2022. The workshop also conducted a set of breakout discussions around the five principal research directions (PRDs) from the 2018 Department of Energy workshop report: 1) define innovative material, device, and architecture requirements driven by applications, algorithms, and software; 2) revolutionize memory and data storage; 3) re-imagine information flow unconstrained by interconnects; 4) redefine computing by leveraging unexploited physical phenomena; 5) reinvent the electricity grid through new materials, devices, and architectures. We tasked each breakout group to consider one primary PRD (and other PRDs as relevant topics arose during discussions) and to address questions such as whether the research community has embraced co-design as a methodology and whether new developments at any level of innovation from materials to programming models requires the research community to reevaluate the PRDs developed back in 2018.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1985

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Buehler, M. G.↗