Total Ionizing Dose Test Report for the AD9364 RF Transceiver
This is a Total Ionizing Dose (TID) test report for the Analog Devices AD9364 RF Transceiver.
complementary metal oxide semiconductor (CMOS)↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A Sub-Threshold Low-Power Integrated Bandpass Filter for Highly-Integrated Spectrum Analyzers
Low-power analog filter banks provide frequency analysis with minimal power and space requirements, making them viable solutions for integrated remote audio- and vibration-sensing applications. Compared with their digital counterparts, analog filter banks are better suited to achieve the lower power consumption necessary for IoT applications, while maintaining high dynamic range and a wide operational frequency range. In this work, the design and implementation of a sub-threshold complementary metal-oxide semiconductor (CMOS) integrated low-power tunable analog filter channel for signal spectrum analysis and signal discrimination is presented. Project specifications required a programmable, high-order, monolithic bandpass filter channel with small chip area, low power consumption, high dynamic range, and wide operational frequency range. The 8th-order filter channel presented in this work provides an effective Q-factor of 4.5 and a minimum dynamic range (DR) of approximately 85 dB, while allowing for tuning across a range of center frequencies from 2 kHz to 100 kHz, with power consumption of a single 8th-order filter channel measured at 256 µW nominally at the highest center frequency. An integrated analog Gm-C filter topology was selected for this application. Functionally, the high-Q bandpass filter transfer function is implemented via four cascaded 2nd-order filter cells, resulting in a single 8th-order filter channel, fabricated in 130-nm 1.2-V CMOS technology, suitable for use in monolithic integrated spectral analysis (MISA1) applications.
Long, Gavin B.↗
A Sub-Threshold Low-Power Integrated Bandpass Filter for Highly-Integrated Spectrum Analyzers
Low-power analog filter banks provide frequency analysis with minimal power and space requirements, making them viable solutions for integrated remote audio- and vibration-sensing applications. Compared with their digital counterparts, analog filter banks are better suited to achieve the lower power consumption necessary for IoT applications. In this work, the design and implementation of a sub-threshold complementary metal-oxide semiconductor (CMOS) integrated low-power tunable bandpass filter channel for signal spectrum analysis and signal discrimination is presented, including performance improvements to stability and precise matching between filter stages. The 8 th -order filter channel achieves an effective Q-factor of 4.5 and dynamic range of 60 dB, has an operational frequency range from 2 kHz to 100 kHz, and consumes 256 µW nominally at the highest center frequency. An integrated analog Gm-C filter topology is selected for this application. Functionally, the high-Q bandpass filter transfer function is implemented via four cascaded 2 nd -order filter cells and is fabricated in 130-nm 1.2-V CMOS technology, making it suitable for use in monolithic integrated spectral analysis (MISA) applications.
Long, Gavin↗
Tunable doping of carbon nanotubes through engineered atomic layer deposition
A carbon nanotube field effect transistor (CNFET), that has a channel formed of carbon nanotubes (CNTs), includes a layered deposit of a nonstoichiometric doping oxide (NDO), such as HfOX, where the concentration of the NDO varies through the thickness of the layer(s). An n-type metal-oxide semiconductor (NMOS) CNFET made in this manner can achieve similar ON-current, OFF-current, and/or threshold voltage magnitudes to a corresponding p-type metal-oxide semiconductor (PMOS) CNFET. Such an NMOS and PMOS can be used to achieve a symmetric complementary metal-oxide semiconductor (CMOS) CNFET design.
Source record↗
Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration
Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.
DeGregorio, Kelly↗
The DUV Stability of Superlattice-Doped CMOS Detector Arrays
No abstract available
molecular beam epitaxy↗
A back-illuminated megapixel CMOS image sensor
In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.
Complementary Metal Oxide Semiconductor imager (CM↗
Camera-on-a-Chip
Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.
Source record↗
Characterization of Advanced Imaging Systems for High-Resolution and Event-Mode Detection
Post-irradiation examination (PIE) is a continually growing field critical to the development of improved nuclear fuels. To characterize these materials, neutron imaging systems are employed and outfitted with, typically, CMOS or CCD cameras - complementary metal oxide semiconductor sensors and charge-couple devices. Imaging systems are a team-effort between the camera, scintillating materials, and object of interest, as a result of neutrons' inherent need to be converted to a detectable signal. High resolution imaging, flash radiography imaging, and event-mode detection systems are three systems undergoing development, construction, and characterization for improved spatial resolution and time-of-flight detection for PIE efforts.
11 - NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗
Prediction and measurement of radiation damage to CMOS devices on board spacecraft
The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.
Cliff, R. A.↗
A room-temperature polarization-sensitive CMOS terahertz camera based on quantum-dot-enhanced terahertz-to-visible photon upconversion
Detection of terahertz (THz) radiation has many potential applications, but presently available detectors are limited in many aspects of their performance, including sensitivity, speed, bandwidth and operating temperature. Most do not allow the characterization of THz polarization states. Recent observation of THz-driven luminescence in quantum dots offers a possible detection mechanism via field-driven interdot charge transfer. Here, we demonstrate a room-temperature complementary metal–oxide–semiconductor THz camera and polarimeter based on quantum-dot-enhanced THz-to-visible upconversion mechanism with optimized luminophore geometries and fabrication designs. Besides broadband and fast responses, the nanoslit-based sensor can detect THz pulses with peak fields as low as 10 kV cm–1. A related coaxial nanoaperture-type device shows a to-date-unexplored capability to simultaneously record the THz polarization state and field strength with similar sensitivity.
77 NANOSCIENCE AND NANOTECHNOLOGY↗
Nonvolatile programmable neural network synaptic array
A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.
Tawel, Raoul↗
High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture
Abstract Recent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.
47 OTHER INSTRUMENTATION↗
Single-Chip T/R Module for 1.2 GHz
A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.
Moussessian, Alina↗
High-bandwidth density silicon photonic resonators for energy-efficient optical interconnects
The growth of artificial intelligence applications demands ever larger and more complex deep learning models, dominating today's—and tomorrow's—data center and high-performance computing systems. While traditional electronics are failing to keep pace with application demands, silicon photonic (SiPh) interconnects have emerged as a necessary technology to support these systems. SiPh-driven wavelength-division multiplexing (WDM) offers a particularly promising path toward supporting incredibly high-aggregate link bandwidth in a compact and efficient form factor. One of the basic building blocks of these integrated WDM interconnects is the SiPh resonator. Their inherent wavelength selectivity and compact footprint allow for efficient data transmission multiplexed across dozens of carrier wavelengths. Used as add-drop (AD) filters, SiPh resonators are critical to constructing integrated tunable wavelength-selective optical circuit switches as well as for demultiplexing the different carrier wavelengths toward independent wavelength-insensitive photodiodes in a dense wavelength-division multiplexing receiver. Resonators in the all-pass (AP) configuration are widespread as well, allowing for wavelength-selective modulation to drive aggregate link bandwidths far beyond the individual channel data rate. Unlike SiPh Mach–Zehnder modulators (MZM), resonant modulators can be driven using low, complementary metal-oxide-semiconductor drive voltages, allowing for tight co-integration between photonic integrated circuits, fabricated with larger process node technologies, and electronic integrated circuits, designed to exploit the advantages of the latest node. To push toward practical peta-scale interconnects, a comprehensive review of SiPh resonators is required, addressing bottlenecks and design constraints at both the architecture and device levels. We first describe the predominant integrated link architectures and identify their limits. We then discuss the device-level design considerations that can be made for both AD and AP configuration resonators to overcome the system level limits with novel resonator device designs. Analytical models and numerical simulation of resonators are validated by experimental measurement of devices fabricated in a commercial 300-mm foundry, showing a clear path toward volume manufacturing. The demonstrated resonant modulators and filters support the feasibility of increasing the aggregate bandwidth of resonator-driven SiPh interconnects into the peta-scale regime.
42 ENGINEERING↗
CMOS Imager Has Better Cross-Talk and Full-Well Performance
A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.
Pain, Bedabrata↗
Multistate resistance in TaN/(Hf,Zr)O 2 /Ta ferroelectric tunnel junctions
Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have emerged as promising non-volatile memory elements for microelectronics, compatible with back end of line (BEOL) complementary–metal–oxide semiconductor fabrication. This study investigates asymmetric electrode TaN/HZO/Ta devices with a 6 nm thick HZO layer as FTJs for multistate resistive memory applications. The individual FTJs exhibit a resistance ratio exceeding 10× when utilized as a binary state device, with pulsing between −1.7 and +1.4 V to set the high resistance state (HRS) and low resistance state (LRS), respectively. Following with reduced write voltage pulses allows the ferroelectric device to operate with a selection of over 32 distinct resistance states (2 5 bits) between the LRS and HRS. This work then explores the stability of the resistance states during write/read pulse cycling, along with the stability of the state after multiple read pulses. Accessing the multibit state shows stability within 50 reads with the binary state remaining stable for more than 4000 reads pulses. With their multistate tunability and versatility, FTJs hold promise as BEOL memory elements for compute-in-memory (CiM) arrays, binary digital memory, or weighted vector matrix multiplication applications with low power consumption during computations.
CMOS↗