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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Rapid Inference of Logic Gate Neural Networks for Anomaly Detection in High Energy Physics

The increasing data rates and complexity of detectors at the Large Hadron Collider (LHC) necessitate fast and efficient machine learning models, particularly for rapid selection of what data to store, known as triggering. Building on recent work in differentiable logic gates, we present a public implementation of a Convolutional Differentiable Logic Gate Neural Network (CLGN). We apply this to detecting anomalies at the Level-1 Trigger at CMS using public data from the CICADA project. We demonstrate that the CLGN achieves physics performance on par with or superior to conventional quantized neural networks. We also synthesize an LGN for a Field-Programmable Gate Array (FPGA) and show highly promising FPGA characteristics, notably zero Digital Signal Processor (DSP) resource usage. This work highlights the potential of logic gate networks for high-speed, on-detector inference in High Energy Physics and beyond.

FOS: Physical sciences↗
DOE OSTI2021

The Digital Mirror Langmuir Probe: Field Programmable Gate Array Implementation of Real-Time Langmuir Probe Biasing

High bandwidth, high spatial resolution measurements of electron temperature, density and plasma potential are valuable for resolving turbulence in the boundary plasma of tokamaks. While conventional Langmuir probes can provide such measurements either their temporal or spatial resolution is limited: the former by the sweep rate necessary for obtaining I-V characteristics and the latter by the need to use multiple electrodes, as is the case in triple and double probe configurations. The Mirror Langmuir Probe (MLP) bias technique overcomes these limitations by rapidly switching the voltage on a single electrode cycling between three bias states, each dynamically optimised for the local plasma conditions. The MLP system on Alcator C-Mod used analog circuitry to perform this function, measuring Te, VF, and Isat at 1.1 MSPS. Recently, a new prototype digital MLP controller has been implemented on a Red Pitaya Field Programmable Gate Array (FPGA) board which reproduces the functionality of the original controller and performs all data acquisition. There is also the potential to provide the plasma parameters externally for use with feedback control systems. The use of FPGA technology means the system is readily customisable at a fraction of the development time and implementation cost. A second Red Pitaya was used to test the MLP by simulating the current response of a physical probe using C-Mod experimental measurements. This project is available as a git repository to facilitate extensibility (e.g. real-time control outputs, more voltage states) and scalability through collaboration.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2016

IonControl v. 1.0

The IonControl software is a set of python scripts and Field-Programmable-Gate-Array (FPGA) code designed to control a trapped ion research experiment. It enables one to generate the pulses (time resolution: 20ns) necessary to control the quantum states of trapped ions and allows one to collect and analyze measurement results from trapped ion systems.

Maunz, Peter↗
DOE OSTI2015

Virtex-5QV Self Scrubber

This HDL code (hereafter referred to as "software") implements circuitry in Xilinx Virtex-5QV Field Programmable Gate Array (FPGA) hardware. This software allows the device to self-check the consistency of its own configuration memory for radiation-induced errors. The software then provides the capability to correct any single-bit errors detected in the memory using the device's inherent circuitry, or reload corrupted memory frames when larger errors occur that cannot be corrected with the device's built-in error correction and detection scheme.

Wojahn, Christopher K.↗
DOE OSTI2017

New controller for high voltage converter modulator at spallation neutron source

The Spallation Neutron Source (SNS) has developed a new control system for the High Voltage Convertor Modulator (HVCM) at the SNS to replace the original control system which is approaching obsolescence. The original system was based on controllers for similar high voltage systems that were already in use [1]. The new controller, based on National Instruments PXI/FlexRIO Field Programmable Gate Array (FPGA) platform, offers enhancements such as modular construction, flexibility and non-proprietary software. The new controller also provides new capabilities like various methods for modulator pulse flattening, waveform capture, and first fault detection. This paper will discuss the design of the system, including the human machine interface, based on lessons learned at the SNS and other projects. It will also discuss performance and other issues related to its operation in an accelerator facility which requires high availability. To date, 73% of the operational HVCMs have been upgraded to with the new controller, and the remainder are scheduled for completion by mid-2017.

Wezensky, Mark W↗
DOE OSTI2018

Solver for hardware based computing

Full-AC load flow constitutes a core computation in power system analysis. A performance gain with a hardware implementation of a sparse-linear solver using a Field Programmable Gate Array (FPGA) is achieved by use of a DC network emulation of the power system bus. Analog Behavioral Models (ABMs) are used in an efficient strategy for designing analog emulation engines for large-scale power system computation. A generator model is also developed using analog circuits for load flow emulation for power system analysis to reduce computation time. The generator model includes reconfigurable parameters using operational transconductance amplifiers (OTAs). The circuit module is used with other reconfigurable circuits, i.e., transmission lines and loads.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Dynamic virtualized field-programmable gate array resource control for performance and reliability

A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Companion Assisted Software Based Remote Attestation in SCADA Networks

Critical infrastructure such as power generation and water distribution systems have become a priority target in cyber warfare because of their recent computerization and introduction to the internet. As a result, Supervisory Control and Data Acquisition (SCADA) system security has become a hot topic in academic and industrial research. Among these topics, Remote Attestation is a security method intended to detect the presence of fileless malware in remote devices as they continue to operate. This allows for the detection of malware in the absence of long-term storage artifacts before symptoms of compromise begin to appear. In general, a trusted device (the verifier) makes a request for evidence of innocence from the untrusted device (the prover). In software-based schemes, the verifier can then measure the delay between its request and the prover’s response. If this delay is greater than the known computational time of the evidence gathering algorithm performed by the prover, then evidence may have been forged. Multi-hop networks often introduce too much network jitter to allow accurate measurement of prover response time, which limits the effectiveness of software based Remote Attestation in a real-world setting. In this work, we introduce a companion device that the verifier can trust to perform a subset of attestation, thereby removing any network jitter. This device is a Field Programmable Gate Array (FPGA) that is physically connected to the prover. We provide a communication protocol between the verifier, prover, and companion. To evaluate our scheme, we simulate it in a common SCADA network environment under normal and heavy traffic loads. Our simulations are performed in the discrete event network simulator NS-3, and we perform statistical analysis over our results to show that our scheme allows for tight timing constraints to be placed on the prover such that the verifier can more easily determine the validity of the evidence that it receives.

Johnson, William A.↗
DOE OSTI2022

Efficient Implementation of Artificial Neural Networks for Sensor Data Analysis Based on a Genetic Algorithm

The reliability of many industrial processes depends on the sensor system. However, these sensors can be affected by noise, perturbations and failures. Hence, sensor monitoring and diagnosis are fundamental to guarantee the quality of an industrial process. Nowadays, artificial neural networks (ANN) are widely used in sensor signal processing and diagnosis. However, those ANNs usually require many artificial neurons, being difficult to implement in software and hardware due to their high computational costs. This paper presents an optimized implementation of artificial neurons in ANNs for sensor data analysis using a Genetic Algorithm (GA). The objective of GA is to find an adequate segmentation to reduce the activation function approximation error. One of the advantages of the proposed approach is that the cost function used in GA considers the effect of factors such as the ANN architecture or the number of bits used in arithmetic operations. The proposed ANN implementation technique aims to get the best possible approximation for a specific ANN architecture, making easier its implementation in software and hardware. Simulation and experimental results using FPGA (Field Programmable Gate Array) prove the advantages of the proposed approach for implementing sensor data analysis systems based on ANNs.

D estefani, André↗
DOE OSTI2023

Machine Learning 5G Attack Detection in Programmable Logic

Machine learning-assisted network security may significantly contribute to securing 5G components. However, machine learning network security inference speeds generally require tens to hundreds of milliseconds thereby introducing significant latency in 5G operations. The inference latency can be reduced by deploying the machine learning model to programmable logic in a field programmable gate array (FPGA) at the cost of a small loss in accuracy. In order to quantify this loss, as well as to establish baseline performance inference speeds for programmable logic implementations, this work explores an autoencoder and a ß-variational autoencoder deployed on two different FPGA evaluation boards and compares accuracy and performance against an NVIDIA A100 GPU implementation. A publicly available 5G dataset containing 10 types of attacks along with normal traffic is introduced as part of the evaluation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2013

Signal Processing Board for Beam Loss Monitors

This paper describes a new VME based machine protection Beam Loss Monitor (BLM) signal processing board designed at Jefferson Lab which features high sensitivity, high resolution, and low cost per channel. This double-wide VME board provides eight-channel signal processing with each channel having linear, logarithmic, and integrating amplifiers that simultaneously provide the optimal signal processing for both machine protection and beam diagnostics. Amplified signals are independently sampled by 16-bit, fast ADCs and then further processed through a Field Programmable Gate Array (FPGA). It also has features of fast shutdown interface (FSD), beam sync interface, built-in-self-test, remotely controlled bias signals, and on-board memory buffer. The initial experimental test shows that the BLM board has fast response (<< 1us) for integrating and wide dynamic range from 10 nA to 1 mA (>50 dB) for logarithmic signals. The board is suitable for signal processing from photomultiplier (PMT) and ion chamber detectors. Notice: Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177. The U.S. Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish or reproduce this manuscript for U.S. Government purposes.

Yan, Jianxun↗
DOE OSTI2015

Artificial Neural Network-Based Monitoring of the Fuel Assembly Temperature Sensor and FPGA Implementation

Numerous methods have been developed around the world to model the dynamic behavior and detect a faulty operating mode of a temperature sensor. In this context, we present in this study a new method based on the dependence between the fuel assembly temperature profile on control rods positions, and the coolant flow rate in a nuclear reactor. This seems to be possible since the insertion of control rods at different axial positions and variations in flow rate of the reactor coolant results in different produced thermal power in the reactor. This is closely linked to the instant fuel rod temperature profile. In a first step, we selected parameters to be used and confirmed the adequate correlation between the chosen parameters and those to be estimated by the proposed monitoring system. In the next step, we acquired and de-noised the data of corresponding parameters, the qualified data is then used to design and train the artificial neural network. The effective data denoising was done by using the wavelet transform to remove a various kind of artifacts such as inherent noise. With the suitable choice of wavelet level and smoothing method, it was possible for us to remove all the non-required artifacts with a view to verify and analyze the considered signal. In our work, several potential mother wavelet functions (Haar, Daubechies, Bi-orthogonal, Reverse Bi-orthogonal, Discrete Meyer and Symlets) were investigated to find the most similar function with the being processed signals. To implement the proposed monitoring system for the fuel rod temperature sensor (03 wire RTD sensor), we used the Bayesian artificial neural network 'BNN' technique to model the dynamic behavior of the considered sensor, the system correlate the estimated values with the measured for the concretization of the proposed system we propose an FPGA (field programmable gate array) implementation. The monitoring system use the correlation. (authors)

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2015

Thomson Scattering Diagnostic Data Acquisition Systems for Modern Fusion Systems

Uniquely designed complex data acquisition system for Thomson scattering diagnostic was developed. It allows recording short duration (3-5 ns) scattered pulses with 2 GHz sampling rate and 10-bit total resolution in oscilloscope mode. The system consists up to 48 photo detector modules with 0- 200 MHz bandwidth, 1-48 simultaneously sampling ADC modules and synchronization subsystem. The photo detector modules are based on avalanche photodiodes (APD) and ultra-low noise trans-impedance amplifiers. ADC modules include fast analog to digital converters and digital units based on the FPGA (Field- Programmable Gate Array) for data processing and storage. The synchronization subsystem is used to form triggering pulses and to organize the simultaneously mode of ADC modules operation. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

High-bandwidth reconfigurable data acquisition card

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Chen, Kai↗
DOE OSTI2017

Qualified display system architecture - 246

There is a need in the nuclear industry for a Qualified Display System (QDS) architecture as described in this paper. The function of the QDS is to process and display Regulatory Guide 1.97 post accident monitoring parameters. The QDS is implemented on the Lockheed Martin Field-Programmable Gate Array (FPGA) based Nuclear Protection and Control (NuPAC) digital platform, coupled with a Qualified Display Controller (QDC) and a Safety Display Unit (SDU). The QDS is designed to meet the requirements of IEEE 603-1991 (endorsed by Regulatory Guide 1.153, Rev. 1), IEEE 497-2002 (endorsed by Regulatory Guide 1.97, Rev. 4), and IEEE 7-4.3.2- 2003 (endorsed by Regulatory Guide 1.152, Rev. 3). The QDS is designed with flexibility such that it can be implemented in an advanced reactor design, Small Modular Reactor (SMR) with any cooling medium, or digital upgrade project for an operating nuclear plant. The QDS has four independent and redundant divisions. Each division has five layers in the architecture: Process variable input signals; Process Protection Logic (PPL); Algorithm Logic (AL), Interface Panel (IP); and Safety Display Unit (SDU). The QDS meets the following design criteria: redundancy, independence, predictability and repeatability, and diversity capability. The QDS architecture also meets the simplicity design principle. The QDS architecture design provides flexibility in the implementation in a plant. The QDS can be implemented in the design of a new advanced plant or as a digital upgrade in an operating plant. (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
DOE OSTI2017

Practical applications of model checking in the finnish nuclear industry - 281

Model checking is a powerful, formal, computer-assisted verification method that can be used to prove that a model of a (hardware or software) system fulfills stated properties. When used right, model checking can prove the correctness of instrumentation and control (I and C) system application logic, be it a software or a field-programmable gate array (FPGA) based design. The verified properties can also address unwanted functionality, making model checking a very effective method for analyzing spurious actuation. Despite the benefits, model checking is still not widely adopted in the verification of I and C systems, one exception being the Finnish nuclear industry. Since 2008, VTT has applied model checking in practical customer work related to the Olkiluoto 3 EPR, Loviisa 1 and 2 VVER-440, and Hanhikivi 1 AES-2006 nuclear power plants, on commission from either the regulator or the utilities. In this paper, we look at how the method has been used in each of these three projects. We also introduce a user-friendly, graphical modelling tool called MODCHK. We then present an overall view of the design issues detected during nine years of customer work, and one practical example. The 100% coverage means that the design errors that are found often relate to scenarios that are otherwise hard to account for (e.g., exact timing of events, or improper operator actions). (authors)

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗