SEARCH · Search NASA

Results for “hardware performance”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 127 records · Page 7

All sources NASA NTRS DOE OSTI

DOE OSTI2025

Performance Evaluation of a Single-Phase Grid-Forming Inverter Through Hardware Experiments

This study conducts hardware experiments to assess the performance of a commercial single-phase grid-forming (GFM) inverter using a purely hardware-based approach. We adhere to a testing protocol for the GFM inverter and enhance it by exploring the transient performance of GFM inverters across various grid dynamic events. Quantifiable performance metrics are established for each testing scenario to gain insights into the performance of the single-phase GFM inverters. Based on the comprehensive tests, the following observations are summarized: 1) The performance of the single-phase GFM inverter is satisfactory, and it is capable of being the islanding master for residence homes when the main grid is gone. 2) For frequency response, the inverter is able to stay connected but cannot inject the needed active power to support the grid. This may be improved by the manufacturer by using droop control. 3) The GFM inverter exhibits harmful transients in voltage and frequency during islanding operation, which can be enhanced by maintaining the same operating points before and after the breaker is open.

black start↗

DOE OSTI2024

Performance Evaluation of a Single-Phase Grid-Forming Inverter Through Hardware Experiments

dynamic performance↗

DOE OSTI2021

Voltage Regulation Performance Evaluation of Distributed Energy Resource Management via Advanced Hardware-in-the-Loop Simulation

This paper evaluates the performance of coordinated control across advanced distribution management systems (ADMS), distributed energy resources (DERs), and distributed energy resource management systems (DERMS) using an advanced hardware-in-the-loop (HIL) platform. This platform provides a realistic laboratory testing environment, including accurate dynamic modeling of a real-world distribution system from a utility partner, real controllers (ADMS and DERMS), physical power hardware (DERs), and standard communications protocols. One grid service—voltage regulation—is evaluated to show the performance of the coordinated grid automation system. The testing results demonstrate that the coordinated DERMS and ADMS system can effectively regulate system voltages within target operation limits using DERs. The realistic laboratory HIL testing results give utilities confidence in adopting the grid automation systems to manage DERs to achieve system-level control and operation objectives (e.g., voltage regulation). This helps utilities mitigate potential risks (e.g., instability) prior to field deployment.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2022

Calibrating the Classical Hardness of the Quantum Approximate Optimization Algorithm

The trading of fidelity for scale enables approximate classical simulators such as matrix product states (MPSs) to run quantum circuits beyond exact methods. A control parameter, the so-called bond dimension $\mathcal{χ}$ for MPSs, governs the allocated computational resources and the output fidelity. Here, we characterize the fidelity for the quantum approximate optimization algorithm by the expectation value of the cost function that it seeks to minimize and find that it follows a scaling law $\mathscr{F}$(ln $\mathcal{χ}$/N), where N is the number of qubits. With ln $\mathcal{χ}$ amounting to the entanglement that a MPS can encode, we show that the relevant variable for investigating the fidelity is the entanglement per qubit. Importantly, our results calibrate the classical computational power required to achieve the desired fidelity and benchmark the performance of quantum hardware in a realistic setup. For instance, we quantify the hardness of performing better classically than a noisy superconducting quantum processor by readily matching its output to the scaling function. Moreover, we relate the global fidelity to that of individual operations and establish its relationship with $\mathcal{χ}$ and N. We sharpen the requirements for noisy quantum computers to outperform classical techniques at running a quantum optimization algorithm in speed, size, and fidelity.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2019

Critical Experiment Design Phase 2 Report for Integral Request 441

This report documents the second phase of critical experiment design (CED-2) conducted as part of integral experiment request (IER) 441. The purpose of IER-441 is to develop a capability to test the epithermal/intermediate cross sections of materials at the Sandia National Laboratories’ (SNL’s) critical experiment facility using low-enriched uranium oxide fuel. This effort determined that the capability can be achieved using a varying number of test samples in a central test region of a hexagonally pitched lattice driven with a more moderated exterior region. The hollow test region can be changed to either contain a pure aluminum wall or a wall that incorporates a cadmium thermal flux filter. This report documents the development of final anticipated critical configurations using tantalum as the test sample material. Using the anticipated critical configurations, estimates of the experimental uncertainties and sensitivities of materials are performed in keeping with the CEdT process. A list of the new hardware necessary to perform the experiment is included.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2014

Enhancement of GridFTP Performance through Network Reservation Integration and Hardware Offloading

Explore the source record for details and available documents.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

A hardware-in-the-loop approach for laboratory performance verification of flexible building equipment in a typical commercial building

The overall objective of the project is to develop datasets that measure the holistic load flexibility performance of a suite of commonly-used commercial building HVAC and thermal storage equipment using a hardware-in-the-loop test method. The development of the software side of the hardware-in-the-loop flexible load testbed is summarized in this paper.

Chen, Zhelun↗

DOE OSTI2022

Milestone Report: Co-Scheduling Applications on Current and Future Architectures

This report evaluates the viability and performance of co-scheduling scientific applications and workloads between CPUs and GPUs on current and future hardware architectures. This study was performed by collecting hardware independent and memory performance characteristics of 6 ECP mini-applications through Byfl and NSight Systems, by measuring the applications’ co-scheduled performance on current node architectures, and by gathering memory bandwidth utilization data with Intel Advisor and nvprof to begin reasoning about the feasibility of co-scheduling applications on future APU architectures.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2016

Verifying quantitative reliability for programs that execute on unreliable hardware

Emerging high-performance architectures are expected to contain unreliable components that may exhibit soft errors, which silently corrupt the results of computations. Full detection and masking of soft errors is challenging, expensive, and, for some applications, unnecessary. For example, approximate computing applications (such as multimedia processing, machine learning, and big data analytics) can often naturally tolerate soft errors. We introduce Rely, a programming language that enables developers to reason about the quantitative reliability of an application—namely, the probability that it produces the correct result when executed on unreliable hardware. Rely allows developers to specify the reliability requirements for each value that a function produces. We perform a static quantitative reliability analysis that verifies quantitative requirements on the reliability of an application, enabling a developer to perform sound and verified reliability engineering. The analysis takes a Rely program with a reliability specification and a hardware specification that characterizes the reliability of the underlying hardware components and verifies that the program satisfies its reliability specification when executed on the underlying unreliable hardware platform. We demonstrate the application of quantitative reliability analysis on six computations implemented in Rely.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Characterizing Output Bottlenecks of a Production Supercomputer: Analysis and Implications

This article studies the I/O write behaviors of the Titan supercomputer and its Lustre parallel file stores under production load. The results can inform the design, deployment, and configuration of file systems along with the design of I/O software in the application, operating system, and adaptive I/O libraries.We propose a statistical benchmarking methodology to measure write performance across I/O configurations, hardware settings, and system conditions. Moreover, we introduce two relative measures to quantify the write-performance behaviors of hardware components under production load. In addition to designing experiments and benchmarking on Titan, we verify the experimental results on one real application and one real application I/O kernel, XGC and HACC IO, respectively. These two are representative and widely used to address the typical I/O behaviors of applications.In summary, we find that Titan’s I/O system is variable across the machine at fine time scales. This variability has two major implications. First, stragglers lessen the benefit of coupled I/O parallelism (striping). Peak median output bandwidths are obtained with parallel writes to many independent files, with no striping or write sharing of files across clients (compute nodes). I/O parallelism is most effective when the application—or its I/O libraries—distributes the I/O load so that each target stores files for multiple clients and each client writes files on multiple targets in a balanced way with minimal contention. Second, our results suggest that the potential benefit of dynamic adaptation is limited. In particular, it is not fruitful to attempt to identify “good locations” in the machine or in the file system: component performance is driven by transient load conditions and past performance is not a useful predictor of future performance. For example, we do not observe diurnal load patterns that are predictable.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2026

Balance of Plant Modeling and Real-Time Hardware-in-the-Loop Integration with the Microreactor Automated Control System

The advent of novel microreactor technology has driven a focused effort to explore safety and efficiency improvements that can be achieved through the use of automated system control. Development of control strategies, especially for initial demonstration, requires an adequate surrogate environment to safely research failure modes and control integration with realistic hardware delay. However, efficiency gains from control strategies are improved when the scope of controller action is expanded to include system-level dynamics such as downstream heat extraction and mass flow. For this reason, a balance-of-plant (BOP) model of a representative microreactor system has been developed using the TRANsient Simulation Framework of Reconfigurable Models library in Modelica. This model captures a reactor and primary NaK coolant loop that represent corresponding system components of the Microreactor Applications Research Validation and EvaLuation (MARVEL) design as well as a secondary coolant loop and heat extraction representative of the Microreactor Agile Non-Nuclear Experimental Test Bed (MAGNET). This model configuration allows for hardware-in-the-loop (HIL) integration with microreactor automated control system (MACS) hardware in real time through a Python-based gRPC client. Real-time simulation of model performance with emulated hardware and communication delay suggests that under independent proportional-integral-derivative control of BOP model drum dynamics and downstream heat extraction, stable power load following is achievable. A slight delay in load following, filtering of high-frequency dynamics, and localized temperature fluctation suggest room for improvement through the development of higher-level control strategies. The simulated coupling of the MAGNET facility lays the groundwork for future digital twin analysis with a coupled MACS-MAGNET HIL demonstration.

McConnell, Jono [ORNL] (ORCID:0000000238984741)↗

DOE OSTI2015

Comparison of Ring-Buffer-Based Packet Capture Solutions

Traditional packet-capture solutions using commodity hardware incur a large amount of overhead as packets are copied multiple times by the operating system. This overhead slows sensor systems to a point where they are unable to keep up with high bandwidth traffic, resulting in dropped packets. Incomplete packet capture files hinder network monitoring and incident response efforts. While costly commercial hardware exists to capture high bandwidth traffic, several software-based approaches exist to improve packet capture performance using commodity hardware.

Barker, Steven Andrew↗

DOE OSTI2018

Data to hardware binding with physical unclonable functions

The various technologies presented herein relate to binding data (e.g., software) to hardware, wherein the hardware is to utilize the data. The generated binding can be utilized to detect whether at least one of the hardware or the data has been modified between an initial moment (enrollment) and a later moment (authentication). During enrollment, an enrollment value is generated that includes a signature of the data, a first response from a PUF located on the hardware, and a code word. During authentication, a second response from the PUF is utilized to authenticate any of the content in the enrollment value, and based upon the authentication, a determination can be made regarding whether the hardware and/or the data have been modified. If modification is detected then a mitigating operation can be performed, e.g., the hardware is prevented from utilizing the data. If no modification is detected, the data can be utilized.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Towards Generic Parallel Programming in Computer Science Education with Kokkos

Parallel patterns, views, and spaces are promising abstractions to capture the programmer's intent as well as the contextual information that can be used by an underlying runtime to efficiently map software to parallel hardware. These abstractions can be valuable in cases where an algorithm must accommodate requirements of code and performance portability across hardware architectures and vendor programming models. Kokkos is a parallel programming model for host- and accelerator architectures that relies on these abstractions and targets these requirements. It consists of a pure C++ interface, a specification, and a programming library. The programming library exposes patterns and types and maps them to an underlying abstract machine model. The abstract machine model offers a generic view of parallel hardware. While Kokkos is gaining popularity in large-scale HPC applications at some DOE laboratories, we believe that the implemented concepts are of interest to a broader audience including academia as they may contribute to a generic, vendor, and architecture-independent education of parallel programming. In this work, we give an insight into the design considerations of this programming model and list important abstractions. Further, we document best practices obtained from giving virtual classes on Kokkos and give pointers to resources that the reader may consider valuable for a lecture on generic parallel programming for students with preexisting knowledge on this matter.

Ciesko, Jan↗

DOE OSTI2020

Analog architectures for neural network acceleration based on non-volatile memory

Analog hardware accelerators, which perform computation within a dense memory array, have the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. Exploiting the intrinsic computational advantages of memory arrays, however, has proven to be challenging principally due to the overhead imposed by the peripheral circuitry and due to the non-ideal properties of memory devices that play the role of the synapse. We review the existing implementations of these accelerators for deep supervised learning, organizing our discussion around the different levels of the accelerator design hierarchy, with an emphasis on circuits and architecture. We explore and consolidate the various approaches that have been proposed to address the critical challenges faced by analog accelerators, for both neural network inference and training, and highlight the key design trade-offs underlying these techniques.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Decomposition of high-rank factorized unitary coupled-cluster operators using ancilla and multiqubit controlled low-rank counterparts

The factorized form of the unitary coupled-cluster (UCC) approximation is one of the most promising methodologies to prepare trial states for strongly correlated systems within the variational quantum eigensolver framework. The factorized form of the UCC Ansatz can be systematically applied to a reference state to generate the desired entanglement. The difficulty associated with such an approach is the requirement of simultaneously entangling a growing number of qubits, which quickly exceeds the hardware limitations of today's quantum machines. In particular, while circuits for singles and double excitations can be performed on current hardware, higher-rank excitations require too many gate operations. In this work, we propose a set of schemes that trade off using extra qubits for a reduced gate depth to decompose high-rank UCC excitation operators into significantly lower depth circuits. These results will remain useful even when fault-tolerant machines are available to reduce the overall state-preparation circuit depth.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Application of Quantum Machine Learning to High Energy Physics Analysis at LHC using IBM Quantum Computer Simulators and IBM Quantum Computer Hardware

Our group pioneers the use of Quantum Machine Learning (QML) on High Energy Physics analysis at LHC. We have successfully employed several QML classification algorithms in the ttH (Higgs production in association with a top quark pair) and Higgs to two muons (Higgs coupling to second generation fermions), two recent LHC flagship physics analysis, on gate-model quantum computer simulators and hardware. The simulation studies have been performed with the IBM Quantum Framework, Google Tensorflow Quantum Framework, and Amazon Braket Framework, and we have achieved good classification performance that is similar to the performances of the classical machine learning methods currently used in LHC physics analyses, classical SVM, classical BDT, and classical deep neural network for example. We have also performed our studies using IBM superconducting quantum computer hardware and the performance is promising and is approaching the performance from IBM quantum simulators. Moreover, we extend our studies to other QML areas such as quantum anomaly detection and quantum generative adversarial, and some preliminary results have been obtained. Also, we have overcome the challenges of intensive computing resources in the cases of large qubits (25 qubits or more) and large numbers of events using NVIDIA cuQuantum with NERSC Perlmutter HPC. Our studies give an example that Quantum Machine Learning performs as well as its classical counterpart for realistic High Energy Physics analysis datasets. Furthermore, our result on noisy quantum hardware provides important validation for the result on noiseless quantum simulators.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2025

CV4Quantum: Reducing the Sampling Overhead in Probabilistic Error Cancellation Using Control Variates

Quasiprobabilistic decompositions (QPDs) play a key role in maximizing the utility of near-term quantum hardware. For example, Probabilistic Error Cancellation (PEC) (an error mitigation technique) and circuit cutting (which enables large quantum computations to be performed on quantum hardware with a limited number of qubits) both involve QPDs. Computations based on QPDs typically incur large sampling overheads that grow exponentially with the number of error-terms mitigated or number of circuit-cuts employed, limiting their practical feasibility. In this work, we adapt the control variates variance reduction technique from the statistics literature in order to reduce the sampling overhead in QPD-based computations. We demonstrate our method using simulation experiments that mimic a realistic PEC scenario. In our experiments, we observed a more than 50% reduction in the number of samples needed to achieve a given precision, in more than 50% of the PEC-based estimations performed in the study when using our approach. We discuss how future research on constructing good control variates can lead to even stronger sampling overhead reduction.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗