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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗
NASA NTRS2011

Effect of Reverse Bias Stress on Leakage Currents and Breakdown Voltages of Solid Tantalum Capacitors

The majority of solid tantalum capacitors are produced by high-temperature sintering of a fine tantalum powder around a tantalum wire followed by electrolytic anodization that forms a thin amorphous Ta2O5 dielectric layer and pyrolysis of manganese nitrite on the oxide to create a conductive manganese dioxide electrode. A contact to tantalum wire is used as anode terminal and to the manganese layer as a cathode terminal of the device. This process results in formation of an asymmetric Ta -- Ta2O5 -- MnO2 capacitor that has different characteristics at forward (positive bias applied to tantalum) and reverse (positive bias applied to manganese cathode) voltages. Reverse bias currents might be several orders of magnitude larger than forward leakage currents so I-V characteristics of tantalum capacitors resemble characteristics of semiconductor rectifiers. Asymmetric I-V characteristics of Ta -- anodic Ta2O5 systems have been observed at different top electrode materials including metals, electrolytes, conductive polymers, and manganese oxide thus indicating that this phenomenon is likely related to the specifics of the Ta -- Ta2O5 interface. There have been multiple attempts to explain rectifying characteristics of capacitors employing anodic tantalum pentoxide dielectrics. A brief review of works related to reverse bias (RB) behavior of tantalum capacitors shows that the mechanism of conduction in Ta -- Ta2O5 systems is still not clear and more testing and analysis is necessary to understand the processes involved. If tantalum capacitors behave just as rectifiers, then the assessment of the safe reverse bias operating conditions would be a relatively simple task. Unfortunately, these parts can degrade with time under reverse bias significantly, and this further complicates analysis of the I-V characteristics and establishing safe operating areas of the parts. On other hand, time dependence of reverse currents might provide additional information for investigation of the processes under reverse bias conditions. In practice, there were instances when, due to unforeseen events, the system operated at conditions when capacitors experience periodically a relatively small reverse bias for some time followed by normal, forward bias conditions. In such a case an assessment should be made on the degree to which these capacitors are degraded by application of low-voltage reverse bias, and whether this degradation can be reversed by normal operating conditions. In this study, reverse currents in different types of tantalum capacitors were monitored at different reverse voltages below 15%VR and temperatures in the range from room to 145 C for up to 150 hours to get better understanding of the degradation process and determine conditions favorable to the unstable mode of operation. The reversibility of RB degradation has been evaluated after operation of the capacitors at forward bias conditions. The effect of reverse bias stress (RBS) on reliability at normal operating conditions was evaluated using highly accelerated life testing at voltages of 1.5VR and 2 VR and by analysis of changes in distributions of breakdown voltages. Possible mechanisms of RB degradation are discussed.

Teverovsky, Alexander A.↗
NASA NTRS2011

Development of Sample Verification System for Sample Return Missions

This paper describes the development of a proof of-concept sample verification system (SVS) for in-situ mass measurement of planetary rock and soil sample in future robotic sample return missions. Our proof-of-concept SVS device contains a 10 cm diameter pressure sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in proximity to an opposing substrate with a narrow gap. The deformation of the membrane makes the gap to be narrower, resulting in increased capacitance between the two nearly parallel plates. Capacitance readout circuitry on a nearby printed circuit board (PCB) transmits data via a low-voltage differential signaling (LVDS) interface. The fabricated SVS proof-of-concept device has successfully demonstrated approximately 1pF/gram capacitance change

Electrodes↗
NASA NTRS2004

Event-Driven Random-Access-Windowing CCD Imaging System

A charge-coupled-device (CCD) based high-speed imaging system, called a realtime, event-driven (RARE) camera, is undergoing development. This camera is capable of readout from multiple subwindows [also known as regions of interest (ROIs)] within the CCD field of view. Both the sizes and the locations of the ROIs can be controlled in real time and can be changed at the camera frame rate. The predecessor of this camera was described in High-Frame-Rate CCD Camera Having Subwindow Capability (NPO- 30564) NASA Tech Briefs, Vol. 26, No. 12 (December 2002), page 26. The architecture of the prior camera requires tight coupling between camera control logic and an external host computer that provides commands for camera operation and processes pixels from the camera. This tight coupling limits the attainable frame rate and functionality of the camera. The design of the present camera loosens this coupling to increase the achievable frame rate and functionality. From a host computer perspective, the readout operation in the prior camera was defined on a per-line basis; in this camera, it is defined on a per-ROI basis. In addition, the camera includes internal timing circuitry. This combination of features enables real-time, event-driven operation for adaptive control of the camera. Hence, this camera is well suited for applications requiring autonomous control of multiple ROIs to track multiple targets moving throughout the CCD field of view. Additionally, by eliminating the need for control intervention by the host computer during the pixel readout, the present design reduces ROI-readout times to attain higher frame rates. This camera (see figure) includes an imager card consisting of a commercial CCD imager and two signal-processor chips. The imager card converts transistor/ transistor-logic (TTL)-level signals from a field programmable gate array (FPGA) controller card. These signals are transmitted to the imager card via a low-voltage differential signaling (LVDS) cable assembly. The FPGA controller card is connected to the host computer via a standard peripheral component interface (PCI).

Monacos, Steve↗
NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗
NASA NTRS2011

Distributed Capacitive Sensor for Sample Mass Measurement

Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane.

Toda, Risaku↗
NASA NTRS2012

High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA

Analog-to-digital converters (ADCs) are used in scientific and communications instruments on all spacecraft. As data rates get higher, and as the transition is made from parallel ADC designs to high-speed, serial, low-voltage differential signaling (LVDS) designs, the need will arise to interface these in field programmable gate arrays (FPGAs). As Xilinx has released the radiation-hardened version of the Virtex-5, this will likely be used in future missions. High-speed serial ADCs send data at very high rates. A de-serializer instantiated in the fabric of the FPGA could not keep up with these high data rates. The Virtex-5 contains primitives designed specifically for high-speed, source-synchronous de-serialization, but as supported by Xilinx, can only support bitwidths of 10. Supporting bit-widths of 12 or more requires the use of the primitives in an undocumented configuration, a non-trivial task. A new SystemVerilog design was written that is simpler and uses fewer hardware resources than the reference design described in Xilinx Application Note XAPP866. It has been shown to work in a Xilinx XC5VSX24OT connected to a MAXIM MAX1438 12-bit ADC using a 50-MHz sample clock. The design can be replicated in the FPGA for multiple ADCs (four instantiations were used for a total of 28 channels).

Taylor, Gregory H.↗
NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗
NASA NTRS2012

SpaceCube Mini

This version of the SpaceCube will be a full-fledged, onboard space processing system capable of 2500+ MIPS, and featuring a number of plug-andplay gigabit and standard interfaces, all in a condensed 3x3x3 form factor [less than 10 watts and less than 3 lb (approximately equal to 1.4 kg)]. The main processing engine is the Xilinx SIRF radiation- hardened-by-design Virtex-5 FX-130T field-programmable gate array (FPGA). Even as the SpaceCube 2.0 version (currently under test) is being targeted as the platform of choice for a number of the upcoming Earth Science Decadal Survey missions, GSFC has been contacted by customers who wish to see a system that incorporates key features of the version 2.0 architecture in an even smaller form factor. In order to fulfill that need, the SpaceCube Mini is being designed, and will be a very compact and low-power system. A similar flight system with this combination of small size, low power, low cost, adaptability, and extremely high processing power does not otherwise exist, and the SpaceCube Mini will be of tremendous benefit to GSFC and its partners. The SpaceCube Mini will utilize space-grade components. The primary processing engine of the Mini is the Xilinx Virtex-5 SIRF FX-130T radiation-hardened-by-design FPGA for critical flight applications in high-radiation environments. The Mini can also be equipped with a commercial Xilinx Virtex-5 FPGA with integrated PowerPCs for a low-cost, high-power computing platform for use in the relatively radiation- benign LEOs (low-Earth orbits). In either case, this version of the Space-Cube will weigh less than 3 pounds (.1.4 kg), conform to the CubeSat form-factor (10x10x10 cm), and will be low power (less than 10 watts for typical applications). The SpaceCube Mini will have a radiation-hardened Aeroflex FPGA for configuring and scrubbing the Xilinx FPGA by utilizing the onboard FLASH memory to store the configuration files. The FLASH memory will also be used for storing algorithm and application code for the PowerPCs and the Xilinx FPGA. In addition, it will feature highspeed DDR SDRAM (double data rate synchronous dynamic random-access memory) to store the instructions and data of active applications. This version will also feature SATA-II and Gigabit Ethernet interfaces. Furthermore, there will also be general-purpose, multi-gigabit interfaces. In addition, the system will have dozens of transceivers that can support LVDS (low-voltage differential signaling), RS-422, or SpaceWire. The SpaceCube Mini includes an I/O card that can be customized to meet the needs of each mission. This version of the SpaceCube will be designed so that multiple Minis can be networked together using SpaceWire, Ethernet, or even a custom protocol. Scalability can be provided by networking multiple SpaceCube Minis together. Rigid-Flex technology is being targeted for the construction of the SpaceCube Mini, which will make the extremely compact and low-weight design feasible. The SpaceCube Mini is designed to fit in the compact CubeSat form factor, thus allowing deployment in a new class of missions that the previous SpaceCube versions were not suited for. At the time of this reporting, engineering units should be available in the summer 2012.

Michael Lin↗
NASA NTRS2012

Lidar Electro-Optic Beam Switch with a Liquid Crystal Variable Retarder

A document discusses a liquid crystal variable retarder, an electro-optic element that changes the polarization of an optical beam in response to a low-voltage electronic signal. This device can be fabricated so that the element creates, among other states, a half-wave of retardance that can be reduced to a very small retardance. When aligned to a polarized source, this can act to rotate the polarization by 90 in one state, but generate no rotation in the other state. If the beam is then incident on a polarization beam splitter, it will efficiently switch from one path to the other when the voltage is applied. The laser beam switching system has no moving parts, improving reliability over mechanical switching. It is low cost, tolerant of high laser power density, and needs only simple drive electronics, minimizing the required system resources.

Baer, James↗
NASA NTRS2013

DOT Transmit Module

The Deep Space Optical Terminal (DOT) transmit module demonstrates the DOT downlink signaling in a flight electronics assembly that can be qualified for deep space. The assembly has the capability to generate an electronic pulse-position modulation (PPM) waveform suitable for driving a laser assembly to produce the optical downlink signal. The downlink data enters the assembly through a serializer/ deserializer (SERDES) interface, and is encoded using a serially concatenated PPM (SCPPM) forward error correction code. The encoded data is modulated using PPM with an inter-symbol guard time to aid in receiver synchronization. Monitor and control of the assembly is via a low-voltage differential signal (LVDS) interface

Quirk, Kevin J.↗
NASA NTRS2013

Multi-Pass Quadrupole Mass Analyzer

Analysis of the composition of planetary atmospheres is one of the most important and fundamental measurements in planetary robotic exploration. Quadrupole mass analyzers (QMAs) are the primary tool used to execute these investigations, but reductions in size of these instruments has sacrificed mass resolving power so that the best present-day QMA devices are still large, expensive, and do not deliver performance of laboratory instruments. An ultra-high-resolution QMA was developed to resolve N2 +/CO+ by trapping ions in a linear trap quadrupole filter. Because N2 and CO are resolved, gas chromatography columns used to separate species before analysis are eliminated, greatly simplifying gas analysis instrumentation. For highest performance, the ion trap mode is used. High-resolution (or narrow-band) mass selection is carried out in the central region, but near the DC electrodes at each end, RF/DC field settings are adjusted to allow broadband ion passage. This is to prevent ion loss during ion reflection at each end. Ions are created inside the trap so that low-energy particles are selected by low-voltage settings on the end electrodes. This is beneficial to good mass resolution since low-energy particles traverse many cycles of the RF filtering fields. Through Monte Carlo simulations, it is shown that ions are reflected at each end many tens of times, each time being sent back through the central section of the quadrupole where ultrahigh mass filtering is carried out. An analyzer was produced with electrical length orders of magnitude longer than its physical length. Since the selector fields are sized as in conventional devices, the loss of sensitivity inherent in miniaturizing quadrupole instruments is avoided. The no-loss, multi-pass QMA architecture will improve mass resolution of planetary QMA instruments while reducing demands on the RF electronics for high-voltage/high-frequency production since ion transit time is no longer limited to a single pass. The QMA-based instrument will thus give way to substantial reductions of the mass of flight instruments.

Prestage, John D.↗
NASA NTRS2014

Absorption Voltages and Insulation Resistance in Ceramic Capacitors with Cracks

Time dependence of absorption voltages (V(sub abs)) in different types of low-voltage X5R and X7R ceramic capacitors was monitored for a maximum duration of hundred hours after polarization. To evaluate the effect of mechanical defects on V(sub abs)), cracks in the dielectric were introduced either mechanically or by thermal shock. The maximum absorption voltage, time to roll-off, and the rate of voltage decrease are shown to depend on the crack-related leakage currents and insulation resistance in the parts. A simple model that is based on the Dow equivalent circuit for capacitors with absorption has been developed to assess the insulation resistance of capacitors. Standard measurements of the insulation resistance, contrary to the measurements based on V(sub abs)), are not sensitive to the presence of mechanical defects and fail to reveal capacitors with cracks.

ceramic capacitor↗
NASA NTRS2015

Film-Evaporation MEMS Tunable Array for Picosat Propulsion and Thermal Control

The Film-Evaporation MEMS Tunable Array (FEMTA) concept for propulsion and thermal control of picosats exploits microscale surface tension effect in conjunction with temperature- dependent vapor pressure to realize compact, tunable and low-power thermal valving system. The FEMTA is intended to be a self-contained propulsion unit requiring only a low-voltage DC power source to operate. The microfabricated thermal valving and very-high-integration level enables fast high-capacity cooling and high-resolution, low-power micropropulsion for picosats that is superior to existing smallsat micropropulsion and thermal management alternatives.

Propulsion↗
NASA NTRS2016

Absorption Voltages and Insulation Resistance in Ceramic Capacitors with Cracks

Time dependence of absorption voltages (Vabs) in different types of low-voltage X5R and X7R ceramic capacitors was monitored for a maximum duration of hundred hours after polarization. To evaluate the effect of mechanical defects on Vabs, cracks in the dielectric were introduced either mechanically or by thermal shock. The maximum absorption voltage, time to roll-off, and the rate of voltage decrease are shown to depend on the crack-related leakage currents and insulation resistance in the parts. A simple model that is based on the Dow equivalent circuit for capacitors with absorption has been developed to assess the insulation resistance of capacitors. Standard measurements of the insulation resistance, contrary to the measurements based on Vabs, are not sensitive to the presence of mechanical defects and fail to reveal capacitors with cracks. Index Terms: Ceramic capacitor, insulation resistance, dielectric absorption, cracking.

cracking↗
NASA NTRS2016

Evaluation of 10V Chip Polymer Tantalum Capacitors for Space Applications

Due to low ESR and safe failure mode, new technology chip polymer tantalum capacitors (CPTC) have gained popularity in the electronics design community, first in commercial applications, and now in hi-rel and space systems. The major drawbacks of these parts are high leakage currents, degradation under environmental stresses, and a relatively narrow temperature range of operating and storage conditions. Several studies have shown that a certain amount of moisture in polymer cathodes is necessary for a normal operation of the parts. This might limit applications of CPTCs in space systems and requires analysis of long-term exposure to deep vacuum conditions on their performance and reliability. High leakage currents and limited maximum operational temperature complicate accelerated testing that is necessary to assess long-term reliability and require new screening and qualification procedures for quality assurance. A better understanding of behavior of CPTCs as compared to traditional, MnO2, capacitors is necessary to develop adequate approaches for QA system for space applications. A specific of CPTCs is that different materials and processes might be used for low-voltage (10 V and less) and high-voltage (above 10 V) capacitors, so performance and degradation processes in these groups require separate analysis. In this work, that is a part of the NASA Electronic Parts and Packaging (NEPP) program, degradation of AC and DC characteristics under environmental stresses at different temperatures and voltages have been studied in nine lots of commercial and automotive grade capacitors rated to 10 V. Results of analysis of leakage currents, high temperature storage (HTS) up to 5000 hrs in vacuum and air at different temperatures, and Highly Accelerated Life Testing (HALT) in the range from 85 C to 145 C are presented. Temperature and voltage acceleration factors were calculated based on approximation of distributions of degradation rates with a general log-linear Weibull model. Mechanisms of degradation and failures, and requirements for screening and qualification testing are discussed.

Tantalum Capacitors↗
NASA NTRS1995

STRV-1B Cryocooler Vibration Suppression

The STRV-1B cryocooler vibration suppression experiment is a satellite flight demonstration of piezo vibration-suppression technology. A very small, tactical stirling-cooler was flown primarily as a vibration source. Two types of piezo actuators were demonstrated. Low-voltage piezo translators were used to move the entire cryocooler so that the tip of the coldfinger stood still. Also, high-voltage ceramic applique was bonded to the base of the coldfinger providing a second actuation method to compare with the translators. three eddy current transducers were used to measure the coldfinger tip motion relative to the experiment case. The eddy current signal drove two types of control systems. A digital adaptive-feed- forward control system was used to cancel the tip motion of the cryocooler in three dimensions. An analog-comb filter controller was also developed to contrast the two techniques. Motion suppression does nothing to suppress the unbalanced forces in the cryocooler, so a triaxial accelerometer measured the vibration of the satellite in response to the cryocooler. Satellite/ground test results from each of the experiment systems are shown and the systems are compared.

STRV-1B↗
DOE OSTI2026

Submodule-Level Decentralized Control for Cascaded Quadruple Active Bridge-Based Medium-Voltage Converters: Preprint

High-power, low-voltage DC (LVDC) loads, such as AI data centers, electric vehicle fast-charging hubs, and hydrogen electrolyzers, are accelerating the deployment of solid-state transformers (SSTs) that directly interface medium-voltage AC (MVAC) to LVDC, streamlining power delivery. This paper proposes a submodule-level decentralized control strategy for an SST comprising a cascaded H-bridge (CHB) active rectifier on the MVAC side and per-module quadruple-active-bridge (QAB) converters on the LVDC side with local controllers. The proposed strategy eliminates the need for high-fidelity, real-time cross-isolation communication by synchronizing all active bridges to a common heartbeat signal and enabling the primary- and secondary-side controllers to generate independent local control signals (phase shifts). The resultant phase shifts naturally govern average and double-line frequency power transfer between active bridges, enabling each side to meet its control objectives using only local measurements. Detailed controller design considerations are presented based on a stability analysis. Comprehensive electromagnetic-transient simulations demonstrate tight DC-link voltage regulation, high-quality grid currents, and robust operation under load transients and grid disturbances, without real-time communication among the submodule controllers. These results indicate that the proposed scheme can significantly enhance the reliability, scalability, and flexibility of cascaded bridge-based medium-voltage converters.

24 POWER TRANSMISSION AND DISTRIBUTION↗