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At least 127 records · Page 7

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NASA NTRS1987

Development and implementation of a programmable telemetry processor

A programmable telemetry processor was designed for the NASA Goddard Space Flight Center in support of the Systems Utilization Enhancement (SUE) upgrade of the NASA tracking stations at Merritt Island, FL, and Bermuda. The processor is an integrated hardware and software system that performs the front-end telemetry synchronization and decommutation functions and provides for application-specific data processing. This paper presents the design, architecture, and features of the microprocessor controlled unit.

Flagg, Howard S.↗

NASA NTRS1995

Prototype development and test results of a continuous ambient air monitoring system for hydrazine at the 10 ppb level

A Hydrazine Vapor Area Monitor (HVAM) system is currently being field tested as a detector for the presence of hydrazine in ambient air. The MDA/Polymetron Hydrazine Analyzer has been incorporated within the HVAM system as the core detector. This analyzer is a three-electrode liquid analyzer typically used in boiler feed water applications. The HVAM system incorporates a dual-phase sample collection/transport method which simultaneously pulls ambient air samples containing hydrazine and a very dilute sulfuric acid solution (0.0001 M) down a length of 1/4 inch outside diameter (OD) tubing from a remote site to the analyzer. The hydrazine-laden dilute acid stream is separated from the air and the pH is adjusted by addition of a dilute caustic solution to a pH greater than 10.2 prior to analysis. Both the dilute acid and caustic used by the HVAM are continuously generated during system operation on an "as needed" basis by mixing a metered amount of concentrated acid/base with dilution water. All of the waste water generated by the analyzer is purified for reuse by Barnstead ion-exchange cartridges so that the entire system minimizes the generation of waste materials. The pumping of all liquid streams and mixing of the caustic solution and dilution water with the incoming sample are done by a single pump motor fitted with the appropriate mix of peristaltic pump heads. The signal to noise (S/N) ratio of the analyzer has been enhanced by adding a stirrer in the MDA liquid cell to provide mixing normally generated by the high liquid flow rate designed by the manufacturer. An onboard microprocessor continuously monitors liquid levels, sample vacuum, and liquid leak sensors, as well as handles communications and other system functions (such as shut down should system malfunctions or errors occur). The overall system response of the HVAM can be automatically checked at regular intervals by measuring the analyzer response to a metered amount of calibration standard injected into the dilute acid stream. The HVAM system provides two measurement ranges (threshold limit value (TLV): 10 to 1000 parts per billion (ppb)/LEAK: 100 ppb to 10 parts per million (ppm)). The LEAK range is created by dilution of the sulfuric acid/hydrazine liquid sample with pure water. This dual range capability permits the analyzer to quantify ambient air samples whose hydrazine concentrations range from 10 ppb to as high as 10 ppm. The laboratory and field prototypes have demonstrated total system response times on the order of 10 to 12 minutes for samples ranging from 10 to 900 ppb in the lLV mode and is greater than 2 minutes for samples ranging from 100 to 1300 ppb in the LEAK mode. Service intervals of over 3 months have been demonstrated for continuous 24 hour/day, 7 day/week usage. The HVAM is made up of a purged cabinet that contains power supplies, RS422 signal transmission capabilities, a UPS, an on-site warning system, and a Line Replaceable Unit (LRU). The LRU includes all of the liquid flow system, the analyzer, the control/data system microprocessor and assorted flow and liquid-level sensors. The LRU is mounted on a track slide system so it can be serviced inplace or totally removed and quickly exchanged with another calibrated unit, thus minimizing analyzer downtime. Once an LRU is removed from an analyzer enclosure, it can be brought to a laboratory facility for complete calibration and periodic maintenance.

Meneghelli, Barry↗

NASA NTRS1996

Development of the Plant Growth Facility for Use in the Shuttle Middeck and Test Units for Ground-Based Experiments

The plant growth facility (PGF), currently under development as a Space Shuttle middeck facility for the support of research on higher plants in microgravity, is presented. The PGF provides controlled fluorescent lighting and the active control of temperature, relative humidity and CO2 concentration. These parameters are designed to be centrally controlled by a dedicated microprocessor. The status of the experiment can be displayed for onboard analysis, and will be automatically archived for post-flight analysis. The facility is designed to operate for 15 days and will provide air filtration to remove ethylene and trace organics with replaceable potassium permanganate filters. Similar ground units will be available for pre-flight experimentation.

Chapman, David K.↗

NASA NTRS1988

A methodology based on reduced complexity algorithm for system applications using microprocessors

The paper considers a methodology on the analysis and design of a minimum mean-square error criterion linear system incorporating a tapped delay line (TDL) where all the full-precision multiplications in the TDL are constrained to be powers of two. A linear equalizer based on the dispersive and additive noise channel is presented. This microprocessor implementation with optimized power of two TDL coefficients achieves a system performance comparable to the optimum linear equalization with full-precision multiplications for an input data rate of 300 baud.

Yan, T. Y.↗

NASA NTRS1978

A versatile microprocessor-controlled hybrid receiver

A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.

Grant, T. L.↗

NASA NTRS2015

Reconfigurable Very Long Instruction Word (VLIW) Processor

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

Velev, Miroslav N.↗

NASA NTRS1995

Implementation of Remote Acquisition and Storage System

The existing system for gathering and processing acoustical test data had several shortcomings and limitations in the areas of microphone array size, sampling rate, and background noise. A new Remote Acquisition and Storage System (RASS) is being designed for applications not suited for the existing acquisition system. One of the first tasks in the design of the RASS was to redesign the microprocessor card of the existing system to include RS-232 serial ports to accept communications through the radio modem used in the RF link. Cost and parts availability comparisons were made between the newly designed board and commercially available models, and a commercially made model was selected. This model was tested for basic I/0 operations. The prototype of the RF telemetry system was set up and tested. Plans are now being developed for integrating the RF telemetry system with the other RASS subsystems.

Hess, Jason R.↗

NASA NTRS2003

Experimental Verification of Electric Drive Technologies Based on Artificial Intelligence Tools

A laboratory implementation of a fuzzy logic-tracking controller using a low cost Motorola MC68HC11E9 microprocessor is described in this report. The objective is to design the most optimal yet practical controller that can be implemented and marketed, and which gives respectable performance, even when the system loads, inertia and parameters are varying. A distinguishing feature of this work is the by-product goal of developing a marketable, simple, functional and low cost controller. Additionally, real-time nonlinearities are not ignored, and a mathematical model is not required. A number of components have been designed, built and tested individually, and in various combinations of hardware and software segments. These components have been integrated with a brushless motor to constitute the drive system. A microprocessor-based FLC is incorporated to provide robust speed and position control. Design objectives that are difficult to express mathematically can be easily incorporated in a fuzzy logic-based controller by linguistic information (in the form of fuzzy IF-THEN rules). The theory and design are tested in the laboratory using a hardware setup. Several test cases have been conducted to confirm the effectiveness of the proposed controller. The results indicate excellent tracking performance for both speed and position trajectories. For the purpose of comparison, a bang-bang controller has been tested. The fuzzy logic controller performs significantly better than the traditional bang-bang controller. The bang-bang controller has been shown to be relatively inaccurate and lacking in robustness. Description of the implementation hardware system is also given.

Rubaai, Ahmed↗

NASA NTRS1980

Flight-deck automation - Promises and problems

The paper analyzes the role of human factors in flight-deck automation, identifies problem areas, and suggests design guidelines. Flight-deck automation using microprocessor technology and display systems improves performance and safety while leading to a decrease in size, cost, and power consumption. On the other hand negative factors such as failure of automatic equipment, automation-induced error compounded by crew error, crew error in equipment set-up, failure to heed automatic alarms, and loss of proficiency must also be taken into account. Among the problem areas discussed are automation of control tasks, monitoring of complex systems, psychosocial aspects of automation, and alerting and warning systems. Guidelines are suggested for designing, utilising, and improving control and monitoring systems. Investigation into flight-deck automation systems is important as the knowledge gained can be applied to other systems such as air traffic control and nuclear power generation, but the many problems encountered with automated systems need to be analyzed and overcome in future research.

Wiener, E. L.↗

NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Irom, Farokh↗

NASA NTRS1992

The Development of an Airborne Information Management System for Flight Test

An airborne information management system is being developed at the NASA Dryden Flight Research Facility. This system will improve the state of the art in management data acquisition on-board research aircraft. The design centers around highly distributable, high-speed microprocessors that allow data compression, digital filtering, and real-time analysis. This paper describes the areas of applicability, approach to developing the system, potential for trouble areas, and reasons for this development activity. System architecture (including the salient points of what makes it unique), design philosophy, and tradeoff issues are also discussed.

Liquid cooling↗

NASA NTRS1992

The Development of an Airborne Information Management System for Flight Test

Flight Testing↗

NASA NTRS1991

The CRAF/Cassini power subsystem - Preliminary design update

A chronology is provided of the rationale leading from the early Mariner spacecraft to the CRAF/Cassini Mariner Mark II power subsystem architecture. The display pathway began with a hybrid including a solar photovoltaic array, a radioisotope thermoelectric generator (RTG), and a battery supplying a power profile with a peak loading of about 300 W. The initial concept was to distribute power through a new solid-state, programmable switch controlled by an embedded microprocessor. As the overall mission, science, and project design matured, the power requirements increased. The design evolved from the hybrid to two RTG plus batteries to meet peak loadings of near 500 W in 1989. Later that year, circumstances led to abandonment of the distributed computer concept and a return to centralized control. Finally, as power requirements continued to grow, a third RTG was added to the design and the battery removed, with the return to the discharge-controller for transients during fault recovery procedures.

Atkins, Kenneth L.↗

NASA NTRS1979

LSA Large Area Silicon Sheet Task Enhanced I.D. Slicing Technology for Silicon Ingots

Development of inside diameter slicing technology to significantly increase the number of useable slices per inch of crystal over industry practice is discussed. The required reduction of both blade and slice thickness is to be accomplished by a combination of three key elements of slicing technology: (1) ingot rotation with minimum exposed blade area; (2) dynamic cutting edge control; and (3) the use of prefabricated insert blades. Design modifications on a slicing saw with microprocessor controls and hardware fabrication to complete this conversion were initiated. Several runs were conducted on the engineering saw incorporating the method of ingot rotation. Ingots with diameters up to six inches were sliced successfully on a production saw.

Walters, D.↗

NASA NTRS1992

Self-checking self-repairing computer nodes using the mirror processor

Circuitry added to fault-tolerant systems for concurrent error deduction usually reduces performance. Using a technique called micro rollback, it is possible to eliminate most of the performance penalty of concurrent error detection. Error detection is performed in parallel with intermodule communication, and erroneous state changes are later undone. The author reports on the design and implementation of a VLSI RISC microprocessor, called the Mirror Processor (MP), which is capable of micro rollback. In order to achieve concurrent error detection, two MP chips operate in lockstep, comparing external signals and a signature of internal signals every clock cycle. If a mismatch is detected, both processors roll back to the beginning of the cycle when the error occurred. In some cases the erroneous state is corrected by copying a value from the fault-free processor to the faulty processor. The architecture, microarchitecture, and VLSI implementation of the MP, emphasizing its error-detection, error-recovery, and self-diagnosis capabilities, are described.

Tamir, Yuval↗

NASA NTRS2003

ASRC Aerospace Corporation Selects Dynamically Reconfigurable Anadigm(Registered Trademark) FPAA For Advanced Data Acquisition System

Anadigm(registered trademark) today announced that ASRC Aerospace Corporation has designed Anadigm's dynamically reconfigurable Field Programmable Analog Array (FPAA) technology into an advanced data acquisition system developed under contract for NASA. ASRC Aerospace designed in the Anadigm(registered trademark) FPAA to provide complex analog signal conditioning in its intelligent, self-calibrating, and self-healing advanced data acquisition system (ADAS). The ADAS has potential applications in industrial, manufacturing, and aerospace markets. This system offers highly reliable operation while reducing the need for user interaction. Anadigm(registered trademark)'s dynamically reconfigurable FPAAs can be reconfigured in-system by the designer or on the fly by a microprocessor. A single device can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. In the case of the ASRC advanced data acquisition system, the FPAA helps ensure that the system will continue to operating at 100% functionality despite changes in the environment, component degradation, and/or component failures.

Mata, Carlos T.↗

NASA NTRS1983

Design, development, and flight test of a demonstration advanced avionics system

Ames Research Center initiated a program in 1975 to provide the critical information required for the design of integrated avionics suitable for general aviation. The program emphasized the use of data busing, distributed microprocessors, shared electronic displays and data entry devices, and improved functional capability. Design considerations included cost, reliability, maintainability, and modularity. As a final step, a demonstration advanced avionics system (DAAS) was designed, built, and flight tested in a Cessna 402, twin engine, general aviation aircraft. A functional description of the DAAS, including a description of the system architecture, is presented and the program and flight test results are briefly reviewed.

Denergy, D. G.↗

NASA NTRS1981

A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles.

Braswell, F. M.↗