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This slide presentation reviews packaging challenges and options for electronic parts. The presentation includes information about non-hermetic packages, space challenges for packaging and complex package variations.
Environmental tests were performed on packaging test structures designed and manufactured for ESA and CNES by 3D PLus ELectronics. The design provided circuit elements that acted as thermal, mechanical and moisture sensors. Other design features showed the compatibility of the packaging with chip passives, bare electronic dice and plastic encapsulated microcircuits packaged together in an innovative, stacked multichip module. The NASA GSFC testing augmented long duration testing on the same units carried out by ESA and CNES. The NASA portion demonstrated packaging stability over temperature, in moisture, with voltage stress, in shock and in vibration environments.
For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk.
Lightweight, high-efficiency solar arrays are required for future deep space missions using high-power Solar Electric Propulsion (SEP). Structural performance metrics for state-of-the art 30-50 kW flexible blanket arrays recently demonstrated in ground tests are approximately 40 kW/cu m packaging efficiency, 150 W/kg specific power, 0.1 Hz deployed stiffness, and 0.2 g deployed strength. Much larger arrays with up to a megawatt or more of power and improved packaging and specific power are of interest to mission planners for minimizing launch and life cycle costs of Mars exploration. A new concept referred to as the Compact Telescoping Array (CTA) with 60 kW/cu m packaging efficiency at 1 MW of power is described herein. Performance metrics as a function of array size and corresponding power level are derived analytically and validated by finite element analysis. Feasible CTA packaging and deployment approaches are also described. The CTA was developed, in part, to serve as a NASA reference solar array concept against which other proposed designs of 50-1000 kW arrays for future high-power SEP missions could be compared.
The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies.
This paper describes the development of a packaged silicon carbide (SiC) based MEMS pressure sensor system designed specifically for a conventional turbofan engine. The electronic circuit is based on a Clapp-type oscillator that incorporates a 6H-SiC MESFET, a SiCN MEMS capacitive pressure sensor, titanate MIM capacitors, wirewound inductors, and thick film resistors. The pressure sensor serves as the capacitor in the LC tank circuit, thereby linking pressure to the resonant frequency of the oscillator. The oscillator and DC bias circuitry were fabricated on an alumina substrate and secured inside a metal housing. The packaged sensing system reliably operates at 0 to 350 psi and 25 to 540C. The system has a pressure sensitivity of 6.8 x 10E-2 MHzpsi. The packaged system shows negligible difference in frequency response between 25 and 400C. The fully packaged sensor passed standard benchtop acceptance tests and was evaluated on a flight-worthy engine.
The microstructure and properties of additively manufactured (AM) metals are strongly dependent on process conditions. Therefore, process-structure-property (PSP) simulations are a useful tool for exploring process parameter space, studying process variations, and quantifying uncertainty in material properties. However, integrating process-structure and structure-property simulations often involves connecting multiple software packages. Each package may use unique data structures and require substantial domain knowledge. This presentation demonstrates PSP simulation capabilities of Materialite, an open-source package developed at NASA Langley Research Center. Materialite simplifies model linkages by using a common data structure and model interface, enabling straightforward simulation across a PSP model chain. Physics-based models, including kinetic Monte Carlo and crystal plasticity, are implemented within the package. The model interface is also intended to simplify implementation of new models and enable integration with external simulation tools. Example use cases include uncertainty quantification with PSP models and GPU-accelerated powder bed fusion AM process models.
This paper reviews the current status of IC and MEMS packaging technology with emphasis on reliability, compares the norm for IC packaging reliability evaluation and identifies challenges for development of reliability methodologies for MEMS, and finally, proposes the use of COTS MEMS in order to start generating statistically meaningful reliability data as a vehicle for future standardization of reliability test methodology for MEMS packaging.
Using newly developed silicon micromachining technology that enables low-loss and highly integrated packaging solutions, we are developing vertically stacked transmitters and receivers at terahertz frequencies that can be used for communication and other terahertz systems. Although there are multiple ways to address the problem of interconnect and packaging solutions at these frequencies, such as system-on-package (SOP), multi-chip modules (MCM), substrate integrated waveguide (SIW), liquid crystal polymer (LCP) based multilayer technologies, and others, we show that deep reactive ion etching (DRIE) based silicon micromachining with vertical integration allows the most effective solutions at terahertz frequencies.
Study of design approaches that are taken toward optimizing the packaging of electronic modules with respect to size, shape, component orientation, interconnections, and structural support. The study does not present a solution to specific packaging problems, but rather the factors to be considered to achieve optimum packaging designs.
The evolution of the thermal design of the Apollo lunar surface experiments package central station from the basic concept to the final flight hardware is discussed, including results of development, prototype, and qualification tests that were used to verify that the flight hardware would operate adequately on the lunar surface. In addition, brief discussions of the thermal design of experiments included in the experiments package are presented. The flight thermal performance is compared with analytical results and thermal-vacuum test results, and design modifications for future lunar surface experiment packages are presented.
Flat conductor cable (FCC) is relatively new, highly promising means for electrical packaging and system integration. FCC offers numerous desirable traits (weight, volume and cost savings, flexibility, high reliability, predictable and repeatable electrical characteristics) which make it extremely attractive as a packaging medium. FCC, today, finds wide application in everything from integration of lunar equipment to the packaging of electronics in nuclear submarines. Described are cable construction and means of termination, applicable specifications and standards, and total FCC systems. A list of additional sources of data is also included for more intensive study.
For optimal packaging of equipment in shallow-cone vehicle toroidal packaging sets center of gravity of equipment forward. Packages are supported on rings within probe structure to provide low center of gravity. System permits interchanging of units for balance control, so minimum of lateral ballast is required.
The relative penalties associated with various techniques for providing an onboard cold environment for storage of perishable food items, and for the development of packaging and vehicle stowage parameters were investigated in terms of the overall food system design analysis of space shuttle. The degrees of capability for maintaining both a 40 F to 45 F refrigerated temperature and a 0 F and 20 F frozen environment were assessed for the following cooling techniques: (1) phase change (heat sink) concept; (2) thermoelectric concept; (3) vapor cycle concept; and (4) expendable ammonia concept. The parameters considered in the analysis were weight, volume, and spacecraft power restrictions. Data were also produced for packaging and vehicle stowage parameters which are compatible with vehicle weight and volume specifications. Certain assumptions were made for food packaging sizes based on previously generated space shuttle menus. The results of the study are shown, along with the range of meal choices considered.
The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.
The structure and use of an Interactive Graphics Packaging Program (IGPP), conceived to apply computer graphics to the design of packaging electronic circuits onto printed circuit boards (PCB), were described. The intent was to combine the data storage and manipulative power of the computer with the imaginative, intuitive power of a human designer. The hardware includes a CDC 6400 computer and two CDC 777 terminals with CRT screens, light pens, and keyboards. The program is written in FORTRAN 4 extended with the exception of a few functions coded in COMPASS (assembly language). The IGPP performs four major functions for the designer: (1) data input and display, (2) component placement (automatic or manual), (3) conductor path routing (automatic or manual), and (4) data output. The most complex PCB packaged to date measured 16.5 cm by 19 cm and contained 380 components, two layers of ground planes and four layers of conductors mixed with ground planes.
Tasks ranging from quick simple plot (which requires only one call to package) to highly sophisticated plots (including motion picture plots) easily generated with basic knowledge of FORTRAN and plot commands. Designers preparing software system that requires plotted output will find this package offers many advantages over standard hardware support packages available.
Adhesives were evaluated to determine if they qualify for application to hybrid microcircuit packages. The effort consisted of the following: (1) seal gold-plated Kovar packages with selective adhesives and determine seal integrity after exposure to temperature humidity environments; (2) seal both gold-plated Kovar and ceramic packages with the four best adhesives identified in (1) and determine seal integrity after exposure to MIL-STD-883A test environments; and (3) subject the best adhesive identified in (2) to a 60 C/98% RH environment and determine susceptibility to moisture permeation. Test results are provided.