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NASA NTRS2012

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Jhabvala, Murzy↗

NASA NTRS2003

Process for Smoothing an Si Substrate after Etching of SiO2

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

Turner, Tasha↗

NASA NTRS1996

Porous silicon carbide (SIC) semiconductor device

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Shor, Joseph S.↗

NASA NTRS1995

Method of fabricating porous silicon carbide (SiC)

Shor, Joseph S.↗

NASA NTRS2022

Patterns and Controls on Island-Wide Aboveground Biomass Accumulation in Second-Growth Forests of Puerto Rico

Understanding the heterogeneity of biomass accumulation in second-growth tropical forests following land use abandonment is important for informing ecosystem carbon models and forest restoration efforts. There is an urgent need for a broad sample of second-growth forests to enhance our knowledge of carbon accumulation in human-dominated landscapes, especially for older forests. Puerto Rico has predominantly second-growth forests, ranging in age from approximately 25 to more than 80 years. We used an island-wide sample of airborne lidar from the NASA Goddard Lidar, Hyperspectral, and Thermal (G-LiHT) Airborne Imager collected on March 2017, forest inventory data, and data on forest age, precipitation, soils, and land use to estimate aboveground biomass stocks in moist and wet, second-growth tropical forests. Biomass accumulation rates in Puerto Rico were lower, on average, than in other Neotropical forests. Median biomass across >16,700 ha of older second-growth forests was 105 Mg ha−1, and sampled biomass rarely surpassed 250 Mg ha−1. Differences in biomass by age were large and persistent across different substrates and land uses, with a plateau in the pattern of island-wide biomass accumulation after about 33 years. A spatial regression model showed that multiple factors were related to biomass accumulation, including time since abandonment, geologic substrate, past land use as coffee or pasture, precipitation, topographic wetness index, and slope. Our findings have important consequences for the total carbon storage and expected climate mitigation benefits of large-scale reforestation efforts, and highlight the value of airborne lidar for quantifying biomass variability in complex tropical landscapes.

Sebastián Martinuzzi↗

NASA NTRS1989

High-power low-threshold graded-index separate confinement heterostructure AlGaAs single quantum well lasers on Si substrates

A high-power low-threshold graded-index separate confinement heterostructure AlGaAs single quantum well laser on Si substrates has been demonstrated for the first time by a hybrid growth of migration-enhanced molecular beam epitaxy followed by metalorganic vapor phase epitaxy. The quantum well laser showed an output power of more than 400 mW per facet under pulsed conditions. A room-temperature threshold current of 300 mA was obtained with a differential quantum efficiency of 40 percent without facet coating. The threshold current density was 550 A/sq cm for a cavity length of 500 microns. These results show the highest peak power reported to date for low-threshold lasers on Si substrates. The full width at half maximum of the far-field pattern parallel to the junction was 6 deg. Threshold current densities as low as 250 A/sq cm were obtained for lasers on GaAs substrates.

Kim, Jae-Hoon↗

NASA NTRS1979

The Development of a Method of Producing Etch Resistant Wax Patterns on Solar Cells

The first quarter of a one-year program to investigate the production of patterned etch resistant wax coatings on solar cell substrates by printing is reported. Master molds for printing plates were produced for the plates. The resist wax is being studied to determine its relevant physical properties. A printing device is currently in design, and material costs are being compiled as first step in a cost analysis task. All phases of the project are proceeding according to schedule. No specific phases are yet completed.

Pastirik, E.↗

NASA NTRS1983

Production of large-area single-crystal wafers of cubic SiC for semiconductor devices

A reproducible process is described for growing a thick single-crystal layer of cubic SiC on a single-crystal Si wafer by chemical vapor deposition. A buffer layer, grown in situ, is used between the cubic SiC and the Si substrate to minimize the effect of lattice mismatch. Layers of up to 34 microns thick and several sq cm in area have been grown. Wafers are obtained by chemically removing the Si substrates from the grown layers. Excellent electron channeling patterns produced by these wafers indicate very good crystal quality. Preliminary electrical measurements have yielded electron mobilities up to 380 sq cm/Vs.

Nishino, S.↗

NASA NTRS1998

Oxygen Impurities and Defects in Epitaxial Layer SiC and SiC Wafer Characterized by Room and Low Temperatures FTIR

SiC as a highly promising semiconducting material has received increasing attention in the last decade. The impurities such as oxygen and hydrogen have a great effect in electronic properties of semiconducting materials. In this study, the FTIR spectra were measured at room temperature (25 C) and low temperature (-70 C) for an n-type SiC substrate, a p-type epitaxial layer SiC, and patterned Ta on a p-type epitaxial layer SiC sample. The oxygen related IR peaks were measured for all three samples at room and low temperatures. The peak at 1105 cm(exp -1) is the result of a substitutional carbon and a interstitial oxygen in SiC. The concentration of the impurity oxygen increases in the SiC epitaxial layer during the CVD and electron beam processes. For the n-type SiC substrate, this peak does not appear. The peak at 905 cm(exp -1) exists in the IR spectra only for two epitaxial layer on p-type SiC substrate samples. This peak is related to oxygen vacancy centers in SiC, which are introduced in the CVD epitaxial growth process. At low temperature, the peak at 1105 cm(exp -1) shifts down and the peak at 905 cm(exp -1) shifts up for the epitaxial layer SiC samples. It can be explained that, at low temperatures, the stress increases due to the distorted bonds. The study shows that FTIR is a very effective method to evaluate low concentration impurities in SiC.

Lu, W. J.↗

NASA NTRS1997

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Raman, Sanjay↗

NASA NTRS1987

Method of making a semiconductor device

There is disclosed herein a method of making a device made up of at least two separate parts each of which is formed of a patterned array with the parts being mounted one on the other, with the patterned arrays of the parts being aligned, such as a CCD imager having a color filter thereon. The two parts are made on separate substrates with a first alignment key being formed on each substrate. The first alignment keys are formed by photolithography using the same mask to form the first alignment keys on each substrate. The various features of each of the parts are then formed on each substrate with each feature being formed by a photolithographic step using a mask which is aligned to a first alignment key so as to align all the features. A second alignment key is formed on each substrate and is positioned on each substrate in the same relationship with a first alignment key. The second alignment keys are of a material and construction so as to be visible when radiation of a desired wavelength is directed through the substrates. A part formed on one of the substrates is placed over a part formed on the other substrate. Radiation is directed through the substrates and the second alignment keys are aligned so as to align the patterned array of the two parts.

Elabd, Hammam↗

NASA NTRS1993

Phase holograms in PMMA with proximity effect correction

Complex computer generated phase holograms (CGPH's) have been fabricated in PMMA by partial e-beam exposure and subsequent partial development. The CGPH was encoded as a sequence of phase delay pixels and written by the JEOL JBX-5D2 E-beam lithography system, a different dose being assigned to each value of phase delay. Following carefully controlled partial development, the pattern appeared rendered in relief in the PMMA, which then acts as the phase-delay medium. The exposure dose was in the range 20-200 micro-C/sq cm, and very aggressive development in pure acetone led to low contrast. This enabled etch depth control to better than plus or minus lambda(sub vis)/60. That result was obtained by exposing isolated 50 micron square patches and measuring resist removal over the central area where the proximity effect dose was uniform and related only to the local exposure. For complex CGPH's with pixel size of the order of the e-beam proximity effect radius, the patterns must be corrected for the extra exposure caused by electrons scattered back up out of the substrate. This has been accomplished by deconvolving the two-dimensional dose deposition function with the desired dose pattern. The deposition function, which plays much the same role as an instrument response function, was carefully measured under the exact conditions used to expose the samples. The devices fabricated were designed with 16 equal phase steps per retardation cycle, were up to 1 cm square, and consisted of up to 100 million 0.3-2.0 micron square pixels. Data files were up to 500 MB long and exposure times ranged to tens of hours. A Fresnel phase lens was fabricated that had diffraction limited optical performance with better than 85 percent efficiency.

Maker, Paul D.↗

NASA NTRS2013

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Toda, Risaku↗

NASA NTRS1979

High density circuit technology

Polyimide dielectric materials were acquired for comparative and evaluative studies in double layer metal processes. Preliminary experiments were performed. Also, the literature indicates that sputtered aluminum films may be successfully patterned using the left-off technique provided the substrate temperature remains low and the argon pressure in the chamber is relatively high at the time of sputtering. Vendors associated with dry processing equipment are identified. A literature search relative to future trends in VLSI fabrication techniques is described.

Wade, T. E.↗

NASA NTRS1983

Acoustooptic pulse-echo transducer system

A pulse-echo transducer system which uses an ultrasonic generating element and an optical detection technique is described. The transmitting transducer consists of a concentric ring electrode pattern deposited on a circular, X-cut quartz substrate with a circular hole in the center. The rings are independently pulsed with a sequence high voltage signals phased in such a way that the ultrasonic waves generated by the separate rings superimpose to produce a composite field which is focused at a controllable distance below the surface of the specimen. The amplitude of the field reflected from this focus position is determined by the local reflection coefficient of the medium at the effective focal point. By processing the signals received for a range of ultrasonic transducer array focal lengths, the system can be used to locate and size anomalies within solids and liquids. Applications in both nondestructive evaluation and biomedical scanning are suggested.

Claus, R. O.↗

NASA NTRS1992

Conductor-backed coplanar waveguide resonators of Y-Ba-Cu-O and Tl-Ba-Ca-Cu-O on LaAlO3

Conductor-backed coplanar waveguide (CBCPW) resonators operating at 10.8 GHz have been fabricated from Tl-Ba-Ca-O (TBCCO) and Y-Ba-Cu-O (YBCO) thin films on LaAlO3. The resonators consist of a coplanar waveguide (CPW) patterned on the superconducting film side of the LaAlO3 substrate with a gold ground plane coated on the opposite side. These resonators were tested in the temperature range from 14 to 106 K. At 77 K, the best of our TBCCO and YBCO resonators have an unloaded quality factor (Qo) 7 and 4 times, respectively, larger than that of a similar all-gold resonator. In this study, the Qo's of the TBCCO resonators were larger than those of their YBCO counterparts throughout the aforementioned temperature range.

Miranda, F. A.↗

NASA NTRS1993

An x-band peeled HEMT amplifier

A discrete peeled high electron mobility transistor (HEMT) device was integrated into a 10 GHz amplifier. The discrete HEMT device interconnects were made using photo patterned metal, stepping from the 10 mil alumina host substrate onto the 1.3 microns thick peeled GaAs HEMT layer, eliminating the need for bond wires and creating a fully integrated circuit. Testing of devices indicate that the peeled device is not degraded by the peel off step but rather there is an improvement in the quantum well carrier confinement. Circuit testing resulted in a maximum gain of 8.5 dB and a return loss minimum of -12 dB.

Young, Paul G.↗

NASA NTRS1995

PZT Thin Film Piezoelectric Traveling Wave Motor

With the development of micro-electro-mechanical systems (MEMS), its various applications are attracting more and more attention. Among MEMS, micro motors, electrostatic and electromagnetic, are the typical and important ones. As an alternative approach, the piezoelectric traveling wave micro motor, based on thin film material and integrated circuit technologies, circumvents many of the drawbacks of the above mentioned two types of motors and displays distinct advantages. In this paper we report on a lead-zirconate-titanate (PZT) piezoelectric thin film traveling wave motor. The PZT film with a thickness of 150 micrometers and a diameter of 8 mm was first deposited onto a metal substrate as the stator material. Then, eight sections were patterned to form the stator electrodes. The rotor had an 8 kHz frequency power supply. The rotation speed of the motor is 100 rpm. The relationship of the friction between the stator and the rotor and the structure of the rotor on rotation were also studied.

Shen, Dexin↗