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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR susceptibility is explored. SEGR evaluation of gamma-irradiated power MOSFETs suggests a non-significant SEGR susceptibility enhancement due to accumulated dose from gamma rays. During SEGR testing, an unexpected enhanced dose effect from heavy-ion irradiation was detected. We demonstrate that this effect could be due to direct ionization by two or more ions at the same channel location. The probability on-orbit for such an occurrence is near-zero given the low heavy-ion fluence over a typical mission lifetime, and did not affect SEGR susceptibility. The results of this work can be used to bound the risk of SEGR in power MOSFETs considered for insertion into spacecraft and instruments.

Lauenstein, Jean-Marie↗
NASA NTRS2004

LERCIP 2004 Summary

This summer I am continuing my project from the previous two summers. My work involves ohmic contacts to N-type silicon carbide (Sic) devices. My mentor, Dr. Robert Okojie, is developing the technology behind high performance sensors and actuators for harsh environments. Sic is useful because it is able to operate at temperatures up to 600 C and it is resistant to radiation damage. This allows sensors and electronics to be placed in new locations, such as inside a jet engine or in space application without using heavy shielding. Ultimately this results in more efficient, smarter engine technology, reduced launch weights for spacecraft, and high power and high temperature electronics. A fundamental part of Sic devices is the ohmic contact. The contact is the interface between the semiconductor (Sic) and external circuitry. The current flowing in and out the devices is through the contact. Ensuring that these contacts remain ohmic (linear I-V behavior) allows us to fabricate devices that do not waste power at the metallurgical junction. Another key part is maintaining a low contact resistance. It is desired to maintain minimum energy loss by avoiding a rectifying electrical characteristic. My project is to develop and implement a testing procedure for measuring the contact resistance while the device is operating at high temperature. It is important to measure the contacts while simulating the true operating environment as closely as possible. For this reason, measurements are taken while the device is heated at intervals up to 600 C in air. To test the long tern reliability of the devices, the high temperature measurements are repeated after heating the sample for long intervals in air. A new set of data is gathered after heating for a total of 100, 200 and then 400 hours. The current as a function of voltage and the contact resistance was measured using the four point probe technique. The four point probe method is chosen because it measures contact resistance while eliminating error due to wire resistance and calibration issues.

DeAngelis, David↗
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗
NASA NTRS1999

Nano-Satellite Avionics

Abstract NASA's Goddard Space Flight Center (GSFC) is currently developing a new class of satellites called the nano-satellite (nano-sat). A major objective of this development effort is to provide the technology required to enable a constellation of tens to hundreds of nano-satellites to make both remote and in-situ measurements from space. The Nano-sat will be a spacecraft weighing a maximum of 10 kg, including the propellant mass, and producing at least 5 Watts of power to operate the spacecraft. The electronics are required to survive a total radiation dose rate of 100 krads for a mission lifetime of two years. There are many unique challenges that must be met in order to develop the avionics for such a spacecraft. The first challenge is to develop an architecture that will operate on the allotted 5 Watts and meet the diverging requirements of multiple missions. This architecture will need to incorporate a multitude of new advanced microelectronic technologies. The microelectronics developed must be a modular and scalable packaging of technology to solve the problem of developing a solution to both reduce cost and meet the requirements of various missions. This development will utilize the most cost effective approach, whether infusing commercially driven semiconductor devices into spacecraft applications or partnering with industry to design and develop low cost, low power, low mass, and high capacity data processing devices. This paper will discuss the nano-sat architecture and the major technologies that will be developed. The major technologies that will be covered include: (1) Light weight Low Power Electronics Packaging, (2) Radiation Hard/Tolerant, Low Power Processing Platforms, (3) High capacity Low Power Memory Systems (4) Radiation Hard reconfiguragble field programmable gate array (rFPGA)

Culver, Harry↗
NASA NTRS1981

Proceedings of the Conference on High-temperature Electronics

The development of electronic devices for use in high temperature environments is addressed. The instrumentational needs of planetary exploration, fossil and nuclear power reactors, turbine engine monitoring, and well logging are defined. Emphasis is place on the fabrication and performance of materials and semiconductor devices, circuits and systems and packaging.

Source record↗
NASA NTRS1983

Semiconductor optoelectronic devices for free-space optical communications

The properties of individual injection lasers are reviewed, and devices of greater complexity are described. These either include or are relevant to monolithic integration configurations of the lasers with their electronic driving circuitry, power combining methods of semiconductor lasers, and electronic methods of steering the radiation patterns of semiconductor lasers and laser arrays. The potential of AlGaAs laser technology for free-space optical communications systems is demonstrated. These solid-state components, which can generate and modulate light, combine the power of a number of sources and perform at least part of the beam pointing functions. Methods are proposed for overcoming the main drawback of semiconductor lasers, that is, their inability to emit the needed amount of optical power in a single-mode operation.

Katz, J.↗
NASA NTRS2016

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Ikpe, Stanley A.↗
NASA NTRSDate not supplied

Assessment of Cryogenic Analog Electronics for Lunar Environment

Assessment of Analog Electronics for Lunar Power Hibernation Non-nuclear robotic spacecraft on the Moon may not reliably operate past the first lunar day due to the subsequent long lunar night with an extreme low temperature range of 50K-100K. To address this concern, the NASA Glenn Research Center is developing a lunar power hibernation protocol that could enable spacecraft to passively survive the lunar night without any additional heating source and then reactivate at lunar dawn. Low cost lunar robotic missions could extend their mission lifetime from a single lunar cycle to potentially many months, thus greatly extending science data gathering and return on investment for commercial missions. This approach centers on evidence that lithium-ion battery cells can recover to full operation after being subjected to cryogenic temperatures. Exploiting this battery capability requires that all spacecraft electronics, including power system and avionics, passively tolerate the extreme cold without degradation. Key elements in the power system will also need to be capable of actively operating in the extreme cold to perform the functions required to restore the system to full operation after solar power returns at lunar dawn. This presentation provides an assessment of extreme-cold tolerance and operational capability of analog electronics where choices in semiconductor material, device type, and circuit fabrication technology has a dramatic impact on circuit behavior and reliability at low temperatures.

Lunar↗
NASA NTRS1986

Hybrid Laser Would Combine Power With Efficiency

Efficient laser system constructed by using two semiconductor lasers to pump neodymium yttrium aluminum garnet (Nd:YAG) device. Hybrid concept allows digital transmission at data rates of several megabits per second with reasonably sized optical aperture of 20 cm. Beams from two GaAs lasers efficiently coupled for pumping Nd:YAG crystal. Combination of lasers exploits best features of each.

Sipes, Donald L., Jr↗
NASA NTRS1972

Development of high temperature, high radiation resistant silicon semiconductors

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Whorl, C. A.↗
NASA NTRS1972

A summary of the research program in the broad field of electronics

Summary reports of research projects covering solid state materials, semiconductors and devices, quantum electronics, plasmas, applied electromagnetics, electrical engineering systems to include control communication, computer and power systems, biomedical engineering and mathematical biosciences.

Source record↗
NASA NTRS2001

Kelvin Probe Measurements on Solar Cells and Other Thin Film Devices

The Kelvin Probe (KP) has been used for years to measure the surface potential of metals and semiconductors. The KP is an elegantly simple but powerful tool invented by Lord Kelvin around the turn of the century. Using changes in surface potentials as a result of changing the intensity and wavelength of illumination, the KP returns data on material parameters such as band gap energies and the energy levels of interface states. We have employed the KP in the study of CdTe-based solar cells and quantum dot-based solar cells, as well as other thin-film devices. We hope eventually that the KP will be used as an in-line testing station for a fabrication process so that unfinished devices that will not meet requirements can be thrown out before the processing is completed, thus saving resources. Results of these studies will be presented.

Delk, John↗
NASA NTRS1982

Polycrystalline silicon availability for photovoltaic and semiconductor industries

Markets, applications, and production techniques for Siemens process-produced polycrystalline silicon are surveyed. It is noted that as of 1982 a total of six Si materials suppliers were servicing a worldwide total of over 1000 manufacturers of Si-based devices. Besides solar cells, the Si wafers are employed for thyristors, rectifiers, bipolar power transistors, and discrete components for control systems. An estimated 3890 metric tons of semiconductor-grade polycrystalline Si will be used in 1982, and 6200 metric tons by 1985. Although the amount is expected to nearly triple between 1982-89, research is being carried out on the formation of thin films and ribbons for solar cells, thereby eliminating the waste produced in slicing Czolchralski-grown crystals. The free-world Si production in 1982 is estimated to be 3050 metric tons. Various new technologies for the formation of polycrystalline Si at lower costs and with less waste are considered. New entries into the industrial Si formation field are projected to produce a 2000 metric ton excess by 1988.

Ferber, R. R.↗
NASA NTRS1980

Semiconductor step-stress testing

Report documents behavior of discrete diodes and transistors in extensive power and temperature overstress tests. Thirty nine devices were tested in groups designated: (1) power overstress, and (2) and (3) temperature overstress. Results are of interest to users of tested components and engineers in conduction of similar tests.

Meeks, H. B.↗
NASA NTRS2009

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Patterson, Richard↗