Search NASA⌕ Search

SEARCH · Search NASA

Results for “system on a chip”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

Fabrication and Qualification of Coated Chip-on-Board Technology for Miniaturized Space Systems

The results of a study carried out in order to manufacture and verify the quality of chip-on-board (COB) packaging technology are presented. The COB, designed for space applications, was tested under environmental stresses, temperature cycling, and temperature-humidity-bias. Both robustness in space applications and in environmental protection on the ground-complete reliability without hermeticity were searched for. The epoxy-parylene combinations proved to be superior to other materials tested.

Maurer, R. H.↗
NASA NTRS2015

Ion Chromatography-on-a-chip for Water Quality Analysis

We report progress towards developing a Micro-Electro-Mechanical Systems (MEMS)- based ion chromatograph (IC) for crewed spacecraft water analysis. This IC-chip is an offshoot of a NASA-funded effort to produce a high performance liquid chromatograph (HPLC)-chip. This HPLC-chip system would require a desalting (i.e. ion chromatography) step. The complete HPLC instrument consists of the Jet Propulsion Labortory's (JPL's) quadrupole ion trap mass spectrometer integrated with a state-of-the-art MEMS liquid chromatograph (LC) system developed by the California Institute of Technology's (Caltech's) Micromachining Laboratory. The IC version of the chip consist of an electrolysis-based injector, a separation column, two electrolysis pumps for gradient generation, mixer, and a built-in conductivity detector. The HPLC version of the chip also includes a nanospray tip. The low instrument mass, coupled with its high analytical capabilities, makes the LC chip ideally suitable for wide range of applications such as trace contaminant, inorganic analytical science and, when coupled to a mass spectrometer, a macromolecular detection system for either crewed space exploration vehicles or robotic planetary missions.

Kidd, R. D.↗
NASA NTRS2001

A Library of Rad Hard Mixed-Voltage/Mixed-Signal Building Blocks for Integration of Avionics Systems for Deep Space

To build the sensor intensive system-on-a-chip for the next generation spacecrafts for deep space, Center for Integration of Space Microsystems at JPL (CISM) takes advantage of the lower power rating and inherent radiation resistance of Silicon on Insulator technology (SOI). We are developing a suite of mixed-voltage and mixed-signal building blocks in Honeywell's SOI process that can enable the rapid integration of the next generation avionics systems with lower power rating, higher reliability, longer life, and enhanced radiation tolerance for spacecrafts such as the Europa Orbiter and Europa Lander. The mixed-voltage building blocks are predominantly for design of adaptive power management systems. Their design centers around an LDMOS structure that is being developed by Honeywell, Boeing Corp, and the University of Idaho. The mixed-signal building blocks are designed to meet the low power, extreme radiation requirement of deep space applications. These building blocks are predominantly used to interface analog sensors to the digital CPU of the next generation avionics system on a chip. Additional information is contained in the original extended abstract.

Mojarradi, M. M.↗
NASA NTRS2012

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Chen, Liang-Yu↗
NASA NTRS1981

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

Aanstoos, J. V.↗
NASA NTRS2004

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

flight computers↗
NASA NTRS2004

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

power switch slice (PSS)↗
NASA NTRS2002

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Ponchak, George E.↗
NASA NTRS1988

System Measures Logic-Gate Delays

Many gates on chip tested automatically. Automatic testing system measures signal-propagation delays of experimental integrated-circuit array of logic gates. Includes controlling computer, counter/time, and feedback-controlled timing-waveform generator. Multiplexer included on integrated-circuit chip with logic-gate array to be tested. Delays measured by system serve as valuable data for design of fast logic and memory chips.

Blaes, Brent R.↗
NASA NTRS1994

Three-Dimensional Vertical-Bloch-Line Memory System

In proposed magnetic memory system without moving parts, data is stored in stack of two-dimensional vertical-Bloch-line (VBL) memory chips or modules. System similar to one described in "Three-Dimensional Magnetic-Bubble Memory System" (NPO-18533). Each VBL module in this memory system silimar to module described in "Vertical-Bloch-Line Memory" (NPO-18467). Advantages include high storage density, high speed, nonvolatility, and insensitivity to ionizing radiation.

Katti, Romney R.↗
NASA NTRS1989

Wiring Viterbi decoders (splitting deBruijn graphs)

A new Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). A key feature of this decoder is a two-level partitioning of the Viterbi state diagram into identical subgraphs. The larger subgraphs correspond to circuit boards, while the smaller subgraphs correspond to Very Large Scale Integration (VLSI) chips. The full decoder is built from identical boards, which in turn are built from identical chips. The resulting system is modular and hierarchical. The decoder is easy to implement, test, and repair because it uses a single VLSI chip design and a single board design. The partitioning is completely general in the sense that an appropriate number of boards or chips may be wired together to implement a Viterbi decoder of any size greater than or equal to the size of the module.

Collins, O.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1994

Cell Libraries

A NASA contract led to the development of faster and more energy efficient semiconductor materials for digital integrated circuits. Gallium arsenide (GaAs) conducts electrons 4-6 times faster than silicon and uses less power at frequencies above 100-150 megahertz. However, the material is expensive, brittle, fragile and has lacked computer automated engineering tools to solve this problem. Systems & Processes Engineering Corporation (SPEC) developed a series of GaAs cell libraries for cell layout, design rule checking, logic synthesis, placement and routing, simulation and chip assembly. The system is marketed by Compare Design Automation.

Source record↗
NASA NTRS2010

NASA Electronic Parts and Packaging (NEPP) Program - Update

This slide presentation reviews the goals and mission of the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs. The program has been supporting NASA for over 20 years. The focus is on the reliability aspects of electronic devices. In this work the program also supports the electronics industry. There are several areas that the program is involved in: Memories, systems on a chip (SOCs), data conversion devices, power MOSFETS, power converters, scaled CMOS, capacitors, linear devices, fiber optics, and other electronics such as sensors, cryogenic and SiGe that are used in space systems. Each of these area are reviewed with the work that is being done in reliability and effects of radiation on these technologies.

LaBel, Kenneth A.↗