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Devices offer switching speeds greater than semiconducting counterparts. High-Tc superconducting field-effect transistors (SUPEFETs) investigated for use as electronic switches in delay-line-type microwave phase shifters. Resemble semiconductor field-effect transistors in some respects, but their operation based on different principle; namely, electric-field control of transition between superconductivity and normal conductivity.
Dark current reduced by energy-discriminating quantum filter. Very long-wavelength-infrared hot-electron transistor developed. Device detects photons at wavelengths around 16 micrometers. Comprises photodector integrated with energy-discriminating quantum filter in multiple-quantum-well structure. Made of variously doped and undoped layers of GaAs (quantum wells) and Al(x)Ga(1-x)As (barriers between wells). In transistor, bound-to-continuum GaAs/Al(x)Ga(1-x)As multiple-quantum-well infrared photodectors (QWIP) serves as photosensitive emitter. Wide quantum well serves as base, and there is thick barrier between base and collector. Combination of barrier and base quantum well acts as energy-discriminating filter: electrons with higher energies pass through filter to collector, those with lower energies blocked and diverted from output-current path through base contact.
The failure of two transistors in the Altitude Switch Assembly for the Solid Rocket Booster followed by two additional failures a year later presented a challenge to failure analysts. These devices had successfully worked for many years on numerous missions. There was no history of failures with this type of device. Extensive checks of the test procedures gave no indication for a source of the cause. The devices were manufactured more than twenty years ago and failure information on this lot date code was not readily available. External visual exam, radiography, PEID, and leak testing were performed with nominal results Electrical testing indicated nearly identical base-emitter and base-collector characteristics (both forward and reverse) with a low resistance short emitter to collector. These characteristics are indicative of a classic failure mechanism called punchthrough. In failure analysis punchthrough refers to an condition where a relatively low voltage pulse causes the device to conduct very hard producing localized areas of thermal runaway or "hot spots". At one or more of these hot spots, the excessive currents melt the silicon. Heavily doped emitter material diffuses through the base region to the collector forming a diffusion pipe shorting the emitter to base to collector. Upon cooling, an alloy junction forms between the pipe and the base region. Generally, the hot spot (punch-through site) is under the bond and no surface artifact is visible. The devices were delidded and the internal structures were examined microscopically. The gold emitter lead was melted on one device, but others had anomalies in the metallization around the in-tact emitter bonds. The SEM examination confirmed some anomalies to be cosmetic defects while other anomalies were artifacts of the punchthrough site. Subsequent to these analyses, the contractor determined that some irregular testing procedures occurred at the time of the failures heretofore unreported. These testing irregularities involved the use of a breakout box and were the likely cause of the failures. There was no evidence to suggest a generic failure mechanism was responsible for the failure of these transistors.
A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.
This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).
We describe work on a wavelength division multiplexing scheme for radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. Using discrete components, we made a two-channel demonstration of this concept and successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.
We present results on wavelength division multiplexing of radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. A two-channel demonstration of this concept using discrete components successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.
The science drivers for the SPIRIT/SPECS missions demand sensitive, fast, compact, low-power, large-format detector arrays for high resolution imaging and spectroscopy in the far infrared and submillimeter. Detector arrays with 10,000 pixels and sensitivity less than 10(exp 20)-20 W/Hz(exp 20)0.5 are needed. Antenna-coupled superconducting tunnel junction detectors with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique when forming arrays. The device consists of an antenna structure to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure currents through tunnel junction contacts to the absorber volume. We will describe optimization of device parameters, and recent results on fabrication techniques for producing devices with high yield for detector arrays. We will also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.
This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.
The work covered in this report has been directed toward the investigation of the irradiation effects of 22 and 240 MeV protons on several transistors, solar cells, resistors, and condensers to be used in the space radiation environment. The experimental data indicated definite detrimental effects on transistors and solar cells but no apparent effects on the types of resistors and condensers tested. The detrimental effects are of two distinct types: transient and permanent.
SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony, concentration was approximately 4 x 10(exp19) per cubic cm. The electron mobility was over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per sq cm, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V(sub DS)) range, with (V(sub DS)) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.
A model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. The model is based on an existing model that incorporates partitioning of the ferroelectric layer to calculate the polarization within the ferroelectric material. The model incorporates several new aspects that are useful to the user. It takes into account the effect of a non-saturating gate voltage only partially polarizing the ferroelectric material based on the existing remnant polarization. The model also incorporates the decay of the remnant polarization based on the time history of the FFET. A gate pulse of a specific voltage; will not put the ferroelectric material into a single amount of polarization for that voltage, but instead vary with previous state of the material and the time since the last change to the gate voltage. The model also utilizes data from FFETs made from different types of ferroelectric materials to allow the user just to input the material being used and not recreate the entire model. The model also allows the user to input the quality of the ferroelectric material being used. The ferroelectric material quality can go from a theoretical perfect material with little loss and no decay to a less than perfect material with remnant losses and decay. This model is designed to be used by people who need to predict the external characteristics of a FFET before the time and expense of design and fabrication. It also allows the parametric evaluation of quality of the ferroelectric film on the overall performance of the transistor.
For high resolution imaging and spectroscopy in the FIR and submillimeter, space observatories will demand sensitive, fast, compact, low-power detector arrays with 104 pixels and sensitivity less than 10(exp -20) W/Hz(sup 0.5). Antenna-coupled superconducting tunnel junctions with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique. The device consists of an antenna to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure current through junctions contacting the absorber. We describe optimization of device parameters, and results on fabrication techniques for producing devices with high yield for detector arrays. We also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.
SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony concentration was approximately 4 x 10(exp 19) per cubic centimeter. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per square centimeter, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V (sub DS)) range, with V (sub DS) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.
Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decision-making ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline (PANi) is an intriguing material because its electrical conductivity can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain, and when combined with polyethylene oxide (PEO), can be formed into nanofibers with diameters ranging from approximately 50 to 500 nm (depending on the deposition conditions). The initial goal of this work was to demonstrate transistor behavior in these nanofibers, thus creating a foundation for future logic devices.
This paper examines various factors in bipolar device construction and design, and discusses their impact on radiation hardness. The intent of the paper is to improve understanding of the underlying mechanisms for practical devices without special test structures, and to provide (1) guidance in ways to select transistor designs that are more resistant to radiation damage, and (2) methods to estimate the maximum amount of damage that might be expected from a basic transistor design. The latter factor is extremely important in assessing the risk that future lots of devices will be substantially below design limits, which are usually based on test data for older devices.
An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.
Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C