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At least 145 records · Page 8

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗

Radio Frequency Field Programable Gate Array Implementation of Reflectometry Cable Monitoring

PNNL has developed an innovative cable testing system that leverages the Xilinx RF System-on-Chip (RFSoC) technology to create a more flexible and capable measurement tool than traditional approaches. The architecture is designed on the ZCU111 development board and takes advantage of the high-speed digital to analog converters (DAC) and analog to digital converters (ADC) to generate and capture digitally synthesized waveforms. The platform allows engineers to easily adjust power, frequency, duration and modulation on the fly rather than being locked into fixed hardware configurations

Tedeschi, Jonathan [Pacific Northwest National Lab↗

slac-epics/devLinuxAdc

EPICS device support for ADCs using the Linux industrial IO (IIO) subsystem

Lorelli, Jeremy [SLAC National Accelerator Laborat↗

DIRECT RF SAMPLING BASED LLRF CONTROL SYSTEM FOR C-BAND LINEAR ACCELERATOR

Low Level RF (LLRF) control systems of linear accel- erators (LINACs) are typically implemented with hetero- dyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Fre- quency System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. This enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without any analogue mixers, which can significantly simplify the system architec- ture. The data converters sample RF signals in higher order Nyquist zones and then up or down convert digitally by the integrated data path in RFSoC. The closed-loop feedback control firmware implemented in FPGA integrated in RF- SoC can process the base-band signal from the ADC data path and calculate the updated phase and amplitude to be up- mixed by the DAC data path. We have developed a C-band LLRF control RFSoC platform with direct RF sampling, which targets Cool Copper Collider (𝐶3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform will be described. We have optimized the configuration of the data converter and characterized performance of them with RF pulses. The test results for some of the key performance parameters for the LLRF platform with our custom solid-state amplifier, such as phase and amplitude stability, will be discussed in this paper.

Liu, C↗

Machine Learning for DUNE Supernova Trigger

One of the major scientific goals of the Deep Underground Neutrino Experiment (DUNE) is to detect and measure the neutrino flux from galactic core-collapse supernovae. These neutrinos, which exist in the low energy range of up to a few tens of MeV and are responsible for carrying away over 99% of the gravitational binding energy of the supernova, provide an opportunity to study the end of life evolution of massive stars, as well as unique properties and interactions of neutrinos. Because galactic supernovae are expected to occur only on the timespan of every few decades, it is crucial that DUNE is able to detect supernova neutrino interactions when they occur. However, detecting these supernova interactions requires sifting through a large amount of data, and DUNE detectors require a trigger to signal when supernova neutrino events occur. Machine learning provides a potential approach to creating this trigger. This project generates ADC and ground truth images of neutrino interactions in a LArTPC detector as simulated by the Model of Argon Reaction Low Energy Yields (MARLEY) to be used for machine learning. The eventual goal of this work is to facilitate DUNE s detection of supernova neutrino interactions by building a machine learning pipeline that will train the trigger algorithm.

Damish, Stephanie↗

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗

Performance and automatic calibration scheme of the waveform sampler in the ETROC2 ASIC chip

The waveform sampler in the CMS ETROC2 chip for LGAD gain aging monitoring is a 2.56-GS/s 12-bit 8x-Interleaved ADC that consists of a coarse SAR stage, and a fine stage. This architecture delivers high performance on a relatively modest 65 nm process, while requires finding up to 24 calibration constants through calibration. We developed an automatic calibration method using charge injection test data. After calibration, the baseline random error is reduced by a factor of 2.5–3 compared to the default calibration, and a 5% charge measurement precision is achieved in 15 fC charge injection tests.

Fu, Tao [Unlisted, US]↗

Apex Study: Compensating Transient Beam Loading in the RHIC 28 MHZ

With the EIC on the way, it is important that developments and strategies are in place to deal with the very high beam currents that the machine will feature. Specifically, the EIC will collide beams of up to 2.5 A, three times the beam current in RHIC. This higher beam current will cause significant voltage transients in the cavity fields which can lead to longitudinal instabilities and beam loss. In anticipation of these negative effects, studies were carried out on the RHIC 28 MHz cavities using newly developed firmware and software to diagnose and combat beam loading. Diagnostic tools such as the bunch-by-bunch (BbyB) ADC firmware and digital network analyzer (DNA) were used to characterize the closed loop system and transient on the cavity voltage magnitude and phase. Then, a one-turn delay feedback (OTFB) and adaptive feed-forward (aFFWD) were used to minimize the transient beam loading. The studies were carried out with beam during 2 accelerator physics experiements (APEXs) using one of the 28 MHz accelerating cavities here at RHIC.

43 PARTICLE ACCELERATORS↗

Development of BPM Electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗

Captan+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗

Short Circuit Detection and Voltage Sense for High Voltage Ionization Tube Power Supplies

Fermilab's PIP-II upgrade requires new rack-mounted power supplies for Beam Loss Monitor (BLM) ionization tubes compatible with the microTCA 4.1 standard, supporting high-side current measurement for short circuit detection, voltage sense telemetry, and low-side current measurement for beam loss readout. This work presents the design and preliminary schematic of such a supply. A resistive current sensing approach was chosen over inductive, optical, and Hall-effect alternatives for its independence from cable length and component availability. A 500 mΩ inline shunt steps the 2 kV common mode voltage down to roughly 70 V, producing a ~27 μV pulse during a short, which is amplified 500x, compared against a 14-bit DAC threshold, and latched to drive a fault line. Voltage sense steps the 2 kV output down at a 1V/1000V ratio, buffers it with a low bias current amplifier, and digitizes it via a 24-bit ADC over SPI. Onboard power is regulated from 12 V down to isolated 5 V and 3.3 V rails, with capacitive isolation on FPGA communication lines. Lumped parameter models were developed for the ionization tube (0.327 nF, 20 to 200 GΩ dynamic resistance) and the RG-58 coaxial cable to support the design. Component selection is complete and a preliminary schematic has been drawn in Altium Designer, forming the foundation for future prototyping and validation.

Yu, Kellen [Cornell U.]↗

Search for Axions in Magnetic White Dwarf Polarization at Lick and Keck Observatories

We present the most sensitive search to date for light axion-like particles with masses below a micro-eV, using spectropolarimetric data collected from the Lick and Keck Observatories. The conversion of optical photons emitted from the surface of a magnetic white dwarf (MWD) into axions in the strong magnetic field around the star induces a nearly wavelength-independent linear polarization in the observed starlight. We analyze the Stokes parameters $(U, Q, I)$ measured with the Kast spectrograph at the Lick Observatory toward the MWDs SDSS J033320+000720 and ZTF J190132+145807, and with the LRISp-ADC instrument at the Keck Observatory toward ZTF J190132+145807, SDSS J002129+150223, and SDSS J100356+053825 to search for this effect. The data show no evidence of axion-induced linear polarization, and we set world-leading constraints on the axion-photon coupling $|g_{aγγ}| \lesssim 1.7 \times 10^{-12} \,\mathrm{GeV}^{-1}$ at the $95\%$ confidence level for masses $m_a \lesssim 2 \times 10^{-7}\,\mathrm{eV}$.

FOS: Physical sciences↗

Simple first order data compression processor concept

Data-compression processing systems based on an analog-to-digital converter /ADC/, includes a qualitative comparator for comparison of the ADC output with a ramp generator, which is connected as a bidirectional binary counter with selective inputs. A bidirectional ramp counter selects the proper ramp through a ramp generator selection network.

Anderson, T. O.↗

Counting digital filter

Overall design of filter combines radix converter with ADC in single functional unit that directly converts analog input to its negative binary representation. Four basic elements of filter are fixed register, shift register, counter, and accumulator.

Zohar, S.↗

Low-light-level integrating video system

System consists of television camera using 25 mm SEC vidicon, low dispersion spectrograph, and digital video image system used for buffer storage of video data during tube readout scanning. Six-bit ADC converts video to digital data which are stored on magnetic tape for future evaluation.

Duncan, B. J.↗

Documentation for the machine-readable character coded version of the SKYMAP catalogue

The SKYMAP catalogue is a compilation of astronomical data prepared primarily for purposes of attitude guidance for satellites. In addition to the SKYMAP Master Catalogue data base, a software package of data base management and utility programs is available. The tape version of the SKYMAP Catalogue, as received by the Astronomical Data Center (ADC), contains logical records consisting of a combination of binary and EBCDIC data. Certain character coded data in each record are redundant in that the same data are present in binary form. In order to facilitate wider use of all SKYMAP data by the astronomical community, a formatted (character) version was prepared by eliminating all redundant character data and converting all binary data to character form. The character version of the catalogue is described. The document is intended to fully describe the formatted tape so that users can process the data problems and guess work; it should be distributed with any character version of the catalogue.

Warren, W. H., Jr.↗

SETI downconverter

The SETI (Search for Extraterrestrial Intelligence) breadboard subsystem was begun in order to develop the technology to efficiently implement a SETI instrument capable of searching wide bandwidth with high resolution. The downconverter covered is the interface hardware between the receiver IF output and ADC used as the input to the spectrum analyzer.

Crow, B.↗