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At least 145 records · Page 8

High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA

Analog-to-digital converters (ADCs) are used in scientific and communications instruments on all spacecraft. As data rates get higher, and as the transition is made from parallel ADC designs to high-speed, serial, low-voltage differential signaling (LVDS) designs, the need will arise to interface these in field programmable gate arrays (FPGAs). As Xilinx has released the radiation-hardened version of the Virtex-5, this will likely be used in future missions. High-speed serial ADCs send data at very high rates. A de-serializer instantiated in the fabric of the FPGA could not keep up with these high data rates. The Virtex-5 contains primitives designed specifically for high-speed, source-synchronous de-serialization, but as supported by Xilinx, can only support bitwidths of 10. Supporting bit-widths of 12 or more requires the use of the primitives in an undocumented configuration, a non-trivial task. A new SystemVerilog design was written that is simpler and uses fewer hardware resources than the reference design described in Xilinx Application Note XAPP866. It has been shown to work in a Xilinx XC5VSX24OT connected to a MAXIM MAX1438 12-bit ADC using a 50-MHz sample clock. The design can be replicated in the FPGA for multiple ADCs (four instantiations were used for a total of 28 channels).

Taylor, Gregory H.↗

Synchronization using pulsed edge tracking in optical PPM communication system

A pulse position modulated (PPM) optical communication system using narrow pulses of light for data transmission requires accurate time synchronization between transmitter and receiver. The presence of signal energy in the form of optical pulses suggests the use of a pulse edge tracking method of maintaining the necessary timing. The edge tracking operation in a binary PPM system is examined, taking into account the quantum nature of the optical transmissions. Consideration is given first to pure synchronization using a periodic pulsed intensity, then extended to the case where position modulation is present and auxiliary bit decisioning is needed to aid the tracking operation. Performance analysis is made in terms of timing error and its associated statistics. Timing error variances are shown as a function of system signal to noise ratio.

Gagliardi, R.↗

Demonstration of intercontinental DSN clock synchronization by VLBI

The prototype system for Deep Space Network clock synchronization by VLBI has been demonstrated to operate successfully over intercontinental baselines in a series of experiments between Deep Space Stations at Madrid, Spain, and Goldstone, California. As predicted by analysis and short baseline demonstration, the system achieves reliable synchronization between 26m and 64m antenna stations with 17 and 37K nominal system temperatures using under one million bits of data from each station. Semi-real-time operation is feasible since this small amount of data can be transmitted to JPL and processed within minutes. The system resolution is 50 to 400ns, depending on the amount of data processed and the source intensity. The accuracy is believed to be comparable to the resolution, although it could be independently confirmed to only about 5 microseconds using LORAN C.

Hurd, W. J.↗

MODIS - Advanced facility instrument for studies of the earth as a system

The Moderate Resolution Imaging Spectrometer (MODIS), a key part of the Earth Observing System planned for the 1990's, is described. The complementary MODIS-T (64 channels) and MODIS-N (40 channels) instruments provide a multispectral observing capability that has application to land, ocean, and atmospheric research. The modules have a 500-1000 meter spatial resolution to accompany a swath width sufficient to provide two-day repeat coverage from a polar-orbiting, sun-synchronous, space-station serviceable platform. High signal-to-noise capability (500/1 or better) and 10-12 bit quantization over the dynamic ranges of the various spectral bands will be provided by the two modules.

Salomonson, V. V.↗

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗

CoNNeCT Baseband Processor Module

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Yamamoto, Clifford K↗

Coding for Communication Channels with Dead-Time Constraints

Coding schemes have been designed and investigated specifically for optical and electronic data-communication channels in which information is conveyed via pulse-position modulation (PPM) subject to dead-time constraints. These schemes involve the use of error-correcting codes concatenated with codes denoted constrained codes. These codes are decoded using an interactive method. In pulse-position modulation, time is partitioned into frames of Mslots of equal duration. Each frame contains one pulsed slot (all others are non-pulsed). For a given channel, the dead-time constraints are defined as a maximum and a minimum on the allowable time between pulses. For example, if a Q-switched laser is used to transmit the pulses, then the minimum allowable dead time is the time needed to recharge the laser for the next pulse. In the case of bits recorded on a magnetic medium, the minimum allowable time between pulses depends on the recording/playback speed and the minimum distance between pulses needed to prevent interference between adjacent bits during readout. The maximum allowable dead time for a given channel is the maximum time for which it is possible to satisfy the requirement to synchronize slots. In mathematical shorthand, the dead-time constraints for a given channel are represented by the pair of integers (d,k), where d is the minimum allowable number of zeroes between ones and k is the maximum allowable number of zeroes between ones. A system of the type to which the present schemes apply is represented by a binary- input, real-valued-output channel model illustrated in the figure. At the transmitting end, information bits are first encoded by use of an error-correcting code, then further encoded by use of a constrained code. Several constrained codes for channels subject to constraints of (d,infinity) have been investigated theoretically and computationally. The baseline codes chosen for purposes of comparison were simple PPM codes characterized by M-slot PPM frames separated by d-slot dead times.

Moision, Bruce↗

Pulsed plasma microthruster for synchronous meteorological satellite /SMS/

Two completely self contained variable thrust flight prototype plasma propulsion systems using solid teflon as propellant were designed, built and laboratory tested. The impulse bit amplitude of each thruster is 25 micro lb-sec. Impulse bits can be provided at rates varying from 50 ppm to 110 ppm. The total impulse capability is 400 lb-sec. Only 23 watts of bus power are required at maximum pulse rate. The system was subjected and passed the required vibration schedule and thermal vacuum test after a minor change in capacitor end face material. A 13 million discharge life test of the system was subsequently performed.

Guman, W. J.↗

Free-Flying Magnetometer Data System

The Free-Flying Magnetometer (FFM) is an autonomous "sensorcraft" developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy sounding rocket mission. This mission was a collaborative project between the University of New Hampshire, Cornell University and JPL. The science goal of the mission was the study of current filamentation phenomena in the northern auroral region through multipoint measurements of magnetic field. The technical objective of the mission was the proof of concept of the JPL FFM design and the demonstration of an in-situ multipoint measurement technique employing many free-flying spacecraft. Four FFMs were successfully deployed from a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. These hockey-puck-sized (80 mm diameter, 38 mm. height, 250 gram mass) free flyers each carry a miniature 3-axis flux-gate magnetometer that output +/- 2 V signals corresponding to a +/- 60,000 nT measurement range for each axis. The FFM uses a synchronized four-channel Sigma(Delta) Analog-to-Digital Converter (ADC) having a dynamic range of +/- 2.5V and converting at a rate of 279 samples/second/channel. Three channels are used to digitize the magnetometer signals to 17-bit (1.144 nT/bit) resolution. The fourth ADC channel is multiplexed for system monitoring of four temperature sensors and two battery voltages. The FFM also contains two sun sensors, a laser diode which emits a fan-shaped beam, a miniature S-band transmitter for direct communication to the ground station antennas, an ultra-stable Temperature Compensated Crystal Oscillator (TCXO) clock, an integrated data subsystem implemented in a Field-Programmable Gate Array (FPGA), a 4 Mbit Static Random Access Memory (SRAM) for data storage and Lithium Thionyl Chloride batteries for power. Communicating commands to the FFM prior to deployment is achieved with an infrared (IR) link. The FFM IR receiver responds to 9-bit pulse coded signals that are generated by an IR Light Emitting Diode (LED) in the payload for turning FFM power on or off and placing the FFM in a test mode or flight mode. The IR links are also used to synchronize (zero) the clocks onboard all the FFMs through a reset pulse originating from the payload GPS receiver that is issued when the FFMs are in flight mode. The FPGA based data subsystem manages continuous data collection from the four ADC channels and sun sensors, formatting and storing the data to SRAM, and controlling downlink transmission. The transmitter is powered only after a 2547 frame SRAM buffer has been filled (approx. 5 minutes of data). The data is Viterbi encoded and sent to the S-band transmitter via a First-In-First-Out (FIFO) buffer who's output is clocked at 100 bits/second. After the 26-second transmission, the transmitter is turned off to reduce noise coupling to the sensitive magnetometer. The data subsystem control consists of a master state machine that performs data flow management and is interfaced through a prioritized interrupt scheme to state machines that service the ADC, sun sensors and transmitter FIFO. Continuous data collection prevents the missing of data during transmission and provides implicit time tagging of the data acquired by the ADC because of synchronization with the TCXO clock.

Blaes, B.↗

Executive summary

The scope of Technology Forecasting for Space Communications is very wide, covering virtually every technology that can directly or indirectly affect space communications. The assigned effort, however, was directed toward a series of studies which individually examined important aspects of space communications and which collectively was interrelated. The contributions of the individual tasks and their interrelationship are indicated. The total effort of the tasks was fairly evenly divided between laser oriented and radio frequency tasks. The investigations show that laser communications have a current state of the art which would allow operational systems to be implemented in the 1975 to 1980 time frame. Further, these systems, when operated over ranges in the order of synchronous ranges (42,000 km)and transmitting data rates of 10 to the 8th power 10 to the 9th power bits per second will have a smaller total weight impact on a spacecraft than do radio systems.

Source record↗

Signal design study for shuttle/TDRSS Ku-band uplink

The adequacy of the signal design approach chosen for the TDRSS/orbiter uplink was evaluated. Critical functions and/or components associated with the baseline design were identified, and design alternatives were developed for those areas considered high risk. A detailed set of RF and signal processing performance specifications for the orbiter hardware associated with the TDRSS/orbiter Ku band uplink was analyzed. Performances of a detailed design of the PN despreader, the PSK carrier synchronization loop, and the symbol synchronizer are identified. The performance of the downlink signal by means of computer simulation to obtain a realistic determination of bit error rate degradations was studied. The three channel PM downlink signal was detailed by means of analysis and computer simulation.

Source record↗

Optical communication with semiconductor laser diodes

Slot timing recovery in a direct detection optical PPM communication system can be achieved by processing the photodetector waveform with a nonlinear device whose output forms the input to a phase lock group. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The rms phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (lambda = 834 nm) and a silicon avalanche photodiode (APD) photodetector and used Q=4 PPM signaling operated at a source data rate of 25 megabits/second. The mathematical model developed to characterize system performance is shown to be in good agreement with actual performance measurements. The use of the recovered slot clock in the receiver resulted in no degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10 to the minus 6 power at received signal energies corresponding to an average of less than 60 detected photons per information bit.

Davidson, F.↗

Slot clock recovery in optical PPM communication systems with avalanche photodiode photodetectors

Slot timing recovery in a direct-detection optical PPM communication system can be achieved by processing the photodetector output waveform with a nonlinear device whose output forms the input to a phase-locked loop. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The rms phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (wavelength = 834 nm) and a silicon avalanche photodiode photodetector. The system used Q = 4 PPM signaling and operated at a source data rate of 25 Mbits/s. The mathematical model developed to compute the rms phase error of the recovered clock is shown to be in good agreement with results of actual measurements of phase errors. The use of the recovered slot clock in the receiver resulted in no significant degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10 to the -6th at a received optical signal energy of 55 detected photons per information bit.

Davidson, Frederic M.↗

Synchronization trigger control system for flow visualization

The use of cinematography or holographic interferometry for dynamic flow visualization in an internal combustion engine requires a control device that globally synchronizes camera and light source timing at a predefined shaft encoder angle. The device is capable of 0.35 deg resolution for rotational speeds of up to 73 240 rpm. This was achieved by implementing the shaft encoder signal addressed look-up table (LUT) and appropriate latches. The developed digital signal processing technique achieves 25 nsec of high speed triggering angle detection by using direct parallel bit comparison of the shaft encoder digital code with a simulated angle reference code, instead of using angle value comparison which involves more complicated computation steps. In order to establish synchronization to an AC reference signal whose magnitude is variant with the rotating speed, a dynamic peak followup synchronization technique has been devised. This method scrutinizes the reference signal and provides the right timing within 40 nsec. Two application examples are described.

Chun, K. S.↗

The effect of timing errors in optical digital systems

The effects of imperfect timing in direct detection (non-coherent) optical binary systems using both PPM and on-off keying for bit transmission are investigated. Particular emphasis is placed on specification of timing accuracy, and an examination of system degradation when this accuracy is not attained. Bit error probabilities are shown as a function of timing errors, from which average error probabilities can be computed for specific synchronization methods. Of significant importance is the presence of a residual, or irreducible error probability in both systems, due entirely to the timing system, that cannot be overcome by the data channel.

Gagliardi, R.↗

A parametric study of the complexity of sequential decoders, volume 2

Plots are presented of complexity versus required signal energy per bit/single-sided noise spectral density to obtain an output probability of error per bit of 0.0001 for an ideal coherent PSK demodulation. Transfer function of convolutional codes and techniques of branch and reference phase synchronization are considered.

Huth, G. K.↗

On the timing problem in optical PPM communications.

Investigation of the effects of imperfect timing in a direct-detection (noncoherent) optical system using pulse-position-modulation bits. Special emphasis is placed on specification of timing accuracy, and an examination of system degradation when this accuracy is not attained. Bit error probabilities are shown as a function of timing errors, from which average error probabilities can be computed for specific synchronization methods. Of significant importance is shown to be the presence of a residual, or irreducible error probability, due entirely to the timing system, that cannot be overcome by the data channel.

Gagliardi, R. M.↗

The effect of timing errors in optical digital systems.

The use of digital transmission with narrow light pulses appears attractive for data communications, but carries with it a stringent requirement on system bit timing. The effects of imperfect timing in direct-detection (noncoherent) optical binary systems are investigated using both pulse-position modulation and on-off keying for bit transmission. Particular emphasis is placed on specification of timing accuracy and an examination of system degradation when this accuracy is not attained. Bit error probabilities are shown as a function of timing errors from which average error probabilities can be computed for specific synchronization methods. Of significance is the presence of a residual or irreducible error probability in both systems, due entirely to the timing system, which cannot be overcome by the data channel.

Gagliardi, R. M.↗