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At least 145 records · Page 8

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DOE OSTI2024

Detuned synchronized waveform averaging for reducing distortions due to sample interleaving

This invention introduces a method for optimally detuning the ratio of analog-to-digital (ADC) sample rate and trigger rate during waveform averaging to minimize the deleterious effects from sample interleaving. A prescription is described for determining the optimal detuning factor for the ADC or trigger rate in any scenario, depending on the number of ADC cores used and the limited tuning resolution of the clock rates for a specific implementation.

42 ENGINEERING↗

DOE OSTI2024

CryoPDK Development for 22nm FDSOI CryoCMOS

Cryogenic Process Design Kits (PDKs) are an indispensable tool in the design of complex integrated circuits across a wide spectrum of applications, from noble element detectors to Quantum Information Science, Superconducting Nanowire Single Photon Detectors (SNSPDs), and precision atomic clocks. The development of PDK-compatible SPICE models is a complex endeavor requiring test structures, measurements, model extraction and fitting. We will present the cryogenic modeling and development of a cryo-PDK for a 22nm FDSOI CMOS process for operation at 3.8 Kelvin.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2024

Multigrid Reduction in Time for Chaotic and Hyperbolic Problems (Final Report)

The coming massive parallelism of exascale computing presents a pressing challenge for the many DOE simulations of time-dependent partial differential equations (PDEs), which typically use traditional sequential time stepping methods. Since this traditional approach is inherently serial, it presents a sequential bottleneck when moving to exascale computing, because future performance gains will come through greater concurrency, not faster clock speeds. Thus, the goal of this work is to research parallelism in time, i.e., methods that compute multiple time values simultaneously, not sequentially. The focus will be on hyperbolic and chaotic problems of interest to DOE, with the goal of enabling scalable simulations of time-dependent hyperbolic and chaotic problems on future architectures. The chosen methodology for solving these problems parallel-in-time is multigrid, because multigrid (when it works) is a powerful, optimal, and scalable solver for discretized PDEs. Multigrid is already commonly used in many DOE simulations for scalably and optimally solving space-only PDE problems. The areas of hyperbolic and chaotic problems are chosen because of their relevance to problems of programmatic interest to DOE. However, these problems are also well-known to be difficult for parallel-in-time methods, with the most common method, parareal, diverging in many cases. The current state of-the-art for parallel-in-time at LLNL is the multigrid reduction in time (MGRIT) XBraid package, which also struggles for such problems, while still showing some improvement over parareal. In summary, new methods are needed for an efficient parallel-in-time scheme for hyperbolic and chaotic problems, and this work shall research promising new multigrid methods in this area. In particular, this work shall continue researching the directions from the current collaboration with Dr. Falgout, which are laid out in the work Toward Parallel in Time for Chaotic Dynamical Systems and showed the first known results of a parallel-in-time speedup for a chaotic problem. This work outlines two key improvements to XBraid for chaotic problems, the so-called “theta” and “delta-correction” methods. Here, these two improvements will be further researched and improved (including with a new relaxation method inspired by on Least Squares Shadowing (LSS)) and explored for more complicated problems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

CAST Technical Bulletin #004: Network Time Protocol Introduction

Network Time Protocol (NTP), as it traditionally generated and widely consumed, is a legacy system with known security vulnerabilities. The vulnerabilities can be mitigated by modern implementations of NTP that use internal and external redundancy for better accuracy and fault tolerance. Precision Time Protocol (PTP) is an alternative that uses master clocks inside secure networks to eliminate the known vulnerabilities of NTP.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2024

2023 Operational Assessment Report: Argonne Leadership Computing Facility

In 2004, the U.S. Department of Energy’s (DOE’s) Advanced Scientific Computing Research (ASCR) program established the Leadership Computing Facility (LCF) with a mission to provide the world’s most advanced computational resources to the open science community. The LCF is a huge investment in the nation’s scientific and technological future, inspired by a growing demand for large-scale computing and its impact on science and engineering. The LCF operates two world-class centers in support of open science at Argonne National Laboratory (Argonne) and at Oak Ridge National Laboratory (Oak Ridge) and deploys diverse machines that are among the most powerful systems in the world today. The LCF ranks among the top U.S. scientific facilities delivering impactful science. The work performed at these centers informs policy decisions and advances innovations in far-reaching areas such as energy assurance, ecological sustainability, and global security. The leadership-class systems at Argonne and Oak Ridge operate around the clock every day of the year. The high level of services these centers provide and the exceptional science they produce justify their existence to the DOE Office of Science and the U.S. Congress

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2024

Bayesian Framework for Predicting and Controlling Metabolic Phenotypes in Microbial System

To improve titers, rates and yields for sucrose production in an engineered strain of Synechococcus elongatus PCC7942, we employed Bayesian metabolic control analysis to transcriptomics and external metabolomics data generated for various phases during the circadian clock. Top overexpression candidates included sodium-dependent bicarbonate transporter (H2cO3_Nat_syn), and UTP—glucose-1-phosphate uridylyltransferase (GALUi). Top repression candidates included Glycogen/starch synthetases, ADP-glucose type (GLCS3), Glutamate racemase (GLUR), and ribonucleoside diphosphate reductase (RNDR1).

60 APPLIED LIFE SCIENCES↗

DOE OSTI2024

Progress in developing a superconducting accelerator for efficient eBeam and X-ray production

The PIP-II Accelerator is an 800 MeV superconducting Linac in the injection chain of the Fermilab accelerator complex. The LLRF systems for the 125 cavities which include a few normal conducting cavities in the warm front-end section, use a variety of LLRF hardware components and sub-systems that are part of the timing and synchronization system. This includes a master oscillator and phase averaging reference line, a beam pattern generator to enable beam transfer between non-harmonic RF systems and beam loading compensation systems synchronized to a start of beam trigger. The timing signals are based on a 650 MHz clock with manchester encoded event information and data provided over optical fiber. The timing and synchronization systems and their performance parameters will be described here.

43 PARTICLE ACCELERATORS↗

DOE OSTI2024

Beam Synchronous for the Rest of Us!

Fermilab’s Tevatron Clock (TCLK) infrastructure has been an integral part of the accelerator control network since the 1980’s. This 10MHz Manchester encoded protocol has enabled flexible, real-time event distribution for thousands of devices connected to the timing network with a high degree of reliability. Forthcoming upgrades to the Fermilab complex (PIP-II, LBNF, ACORN) necessitate higher levels of precision to maintain inter-bunch timing for Instrumentation and Control purposes. This presents as an opportunity to refine the event distribution protocol for tighter synchronization between machines, experiments, and eventually far-site operations. This paper outlines a method by which beam-synchronous events may be distributed through asynchronous serial protocols via integration with local LLRF and global PPS reference signals. This method is ideal for synchrotron machines with aggressive frequency sweeps (such as Fermilab's 38~53MHz Booster) and allows for precision timing to be maintained across machines without specialized hardware.

43 PARTICLE ACCELERATORS↗

DOE OSTI2024

Timing and Synchronization in the LLRF systems of the Fermilab PIP-II Linac

Varghese, Philip↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

DOE OSTI2025

Smart Contracts for Power Grid Applications Using the Advanced DLT Cyber Grid Guard Testbed

In this study is presented two power system applications with distributed ledger technology (DLT) and smart contracts (SC) that were assessed in a Cyber-Grid-Guard System (CGGS) advanced testbed, with protective relays, power meters, communication devices, DLT devices, synchronized time source, clock displays and real time simulator. This CGGS testbed was set in the Advanced Protection Lab, 252 lab space of the Grid Research Integration and Deployment Center (GRID- C), at Oak Ridge National Laboratory. In power grids, customer-owned distributed energy resources (DERs) are more frequent than in the past, and the numbers of points of interconnection (POI) with customer-owned DERs have increased. Disruptive operation from DERs presents a risk to grid operations, and protective relays located at the POI are used to isolate out-of-tolerance or poorly behaving of DERs. Ensuring the integrity of data from the relays at the POI, and DLT could enhance the security of the power grids. The first application is a SC to define and control the allowable total power factor (TPF) of the DER (wind farm) output, and the terms of the SC are implemented using DLT with a CGGS for a customer-owned DER. The TPF SC was implemented by the CGGS using DLT. The experimental model was performed with a real-time simulator using a CGGS and relay in-the-loop. The data collected from the CGGS were used to execute the TPF SC. The TPF limits were between +0.9 and +1.0, and the breakers’ operation in the POI was controlled by the relay using the SC. The events were collected from the real-time simulator, CGGS, and SEL 700GT relay to validate a successful application of the TPF SC using DLT. The second application is a SC to measure and control the allowable voltage service limits (VSL) by the CGGS using DLT. The tests were performed by using a real-time simulator, CGGS and relay in-the-loop. The data was collected from the CGGS that executed the SC. The main constraints were defined based on ANSI C84.1 service voltage limits, and the operation of the breakers in the POI. The events were collected from the CGGS, and SEL 700GT relay to assess a successful operation of the VSL SC using DLT.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗

DOE OSTI2025

Secure NTP Implementation for Power System Synchronization

Network Time Protocol (NTP), originally developed in the 1980s, remains one of the most widely adopted protocols for synchronizing clocks over Internet Protocol (IP)-based networks. It distributes time with millisecond-level accuracy across Ethernet-based systems and continues to be a standard in both enterprise and operational technology environments.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Ion Traps and Packaging for Heterogenous Integration - Chimera

Microfabricated surface ion traps and silicon-based photonics are critical technologies for scaling quantum systems. Current ion trap architectures face scalability and integration challenges due to limitations in optical access, fabrication techniques, and material compatibility. State-of-the-art quantum computers and atomic clocks are investigating monolithic integration, which necessitates custom traps for each ion species and has not overcome the integration hurdles presented by merging these technologies. The Chimera (Ion Traps and Packaging for Heterogeneous Integration) project proposes a novel approach utilizing heterogeneous integration (HI) of ion traps and photonic circuits. This separation of components allows for flexibility in ion trap design and reduces fabrication compromises. The Chimera project specifically designed an ion trap to interface vertically with a separately fabricated waveguide chip and demonstrates the first steps to integrating them at the packaging level. The ion trap features a large area of removed silicon, allowing the photonics chip outputs closer to the ion trap, improving alignment and packaging processes. The alignment must be accurate to < 1 µm to ensure that the light from the waveguide can overlap with the trapping region. This fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. By combining separate chips, we demonstrate a new path for scaling trapped ion technology that is less reliant on monolithic integration. We successfully fabricated a trap with a large area of oxide removed, resulting in a region thinned to about 40 µm, a key milestone toward successful integration.

42 ENGINEERING↗

DOE OSTI2025

Simultaneous Celestial Navigation

GPS technology is used in a multitude of applications around the world for navigation. However, GPS can be contested or denied and thus alternatives to GPS are needed for positioning in high-consequence systems. This project investigates a non-RF based method to produce an estimated geolocation using stellar/celestial measurements in combination with measurements from inclinometers and a real time clock. The initial iteration of this method, developed in FY20/21, achieved an estimated location accuracy within approximately 3 kilometers of the true location with a 3-sigma bound of about 8 kilometers. The next iteration aims to enhance this technology further, targeting an estimation accuracy within 100 meters of the true location, representing a 30-fold improvement over the initial method.

42 ENGINEERING↗

DOE OSTI2025

CSP Plant Optimization Study for the California Power Market (“CalCSP”) (Final Technical Report)

Concentrating Solar Power (CSP) with thermal energy storage offers a unique and strategic opportunity to support California’s clean energy transition. Unlike photovoltaic (PV) systems, CSP with thermal storage can generate electricity after sunset and during periods of high demand, making it a valuable complement to intermittent renewable resources. CSP also provides synchronous, inertia-contributing generation, long-duration storage, and flexible dispatch—capabilities increasingly important as thermal plants retire. This report summarizes the findings of the CSP Plant Optimization Study for the California Power Market or “CalCSP study,” which evaluated the technical, economic, environmental, and policy factors that influence the deployment of CSP technologies in California. The CalCSP study was conducted to assess how CSP can contribute to California’s long-term decarbonization goals while enhancing grid reliability, supporting local economic development, and making efficient use of land and transmission resources. It draws on detailed modeling of CSP performance and costs, site suitability analysis, policy reviews, and stakeholder engagement across utilities, regulators, developers, and community organizations. The analysis focuses on mature molten-salt tower technology and incorporates lessons learned from the global CSP fleet, distinguishing today’s CSP from earlier first-of-a-kind projects in the U.S. The findings support a more prominent role for CSP in California’s evolving clean energy landscape. With strategic planning, targeted policy support, and continued cost improvements, CSP can complement PV and batteries to deliver reliable, around-the-clock clean electricity—especially in areas with high solar resource and constrained grid capacity.

14 SOLAR ENERGY↗

DOE OSTI2025

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗

DOE OSTI2025

Development of BPM Electronics for PIP-II at Fermilab

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability is validated through dedicated testing.

Liu, Shengli [Fermilab] (ORCID:0009000128436936)↗