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Template for use in trimming leads on production wiring boards is low-cost means for eliminating rejections for short leads and improving lead-strength uniformity. Template is simply unclad piece of printed-circuit board material that is drilled using same drill control tape used in making original production board. Revisions in component layout of board can therefore be made simultaneously in template.
Measurement of atmospheric water vapor is very important for understanding the Earth's climate and water cycle. The remote sensing Differential Absorption Lidar (DIAL) technique is a powerful method to perform such measurement from aircraft and space. This thesis describes a new advanced detection system, which incorporates major improvements regarding sensitivity and size. These improvements include a low noise advanced avalanche photodiode detector, a custom analog circuit, a 14-bit digitizer, a microcontroller for on board averaging and finally a fast computer interface. This thesis describes the design and validation of this new water vapor DIAL detection system which was integrated onto a small Printed Circuit Board (PCB) with minimal weight and power consumption. Comparing its measurements to an existing DIAL system for aerosol and water vapor profiling validated the detection system.
The Background Imaging of Cosmic Extragalactic Polarization (BICEP)/Keck (BK) collaboration is currently leading the quest for the highest-sensitivity measurements of the polarized cosmic microwave background (CMB) anisotropies on a degree scale with a series of cryogenic telescopes, of which BICEP Array (BA) is the latest Stage-3 upgrade with a total of ~ 32,000 detectors. The instrument comprises 4 receivers spanning 30–270 GHz, with the low-frequency 30/40 GHz deployed to the South Pole Station in late 2019. The full complement of receivers is forecast to set the most stringent constraints on the tensor-to-scalar ratio r. Building on these advances, the overarching small-aperture telescope concept is already being used as the reference for further Stage-4 experiment design. This paper describes the development of the BICEP Array 150 GHz detector module and its fabrication requirements, with highlights on the high-density time division multiplexing (TDM) design of the cryogenic circuit boards. The low-impedance wiring required between the detectors and the frst stage of superconducting quantum interference device amplifers is crucial to maintaining a stable bias current on the detectors. Here, a novel multilayer FR4 Printed Circuit Board with superconducting traces, capable of reading out up to 648 detectors, is detailed along with its validation tests. An ultra-high-density TDM detector module concept we developed for a CMB-S4-like experiment that allows up to 1920 detectors to be read out is also presented. TDM has been chosen as the detector readout technology for the Cosmic Microwave Background Stage-4 (CMB-S4) experiment based on its proven low-noise performance, predictable costs, and overall maturity of the architecture. The heritage for TDM is rooted in mm- and sub-mm-wave experiments dating back 20 years and has since evolved to support a multiplexing factor of 64x in Stage-3 experiments.
Techniques appropriate to boards containing CMOS circuits detailed. Document presents procedure for applying thin conformal coating to such electronic assemblies as printed-circuit boards and wire-wrapped boards. Coating is from 1 to 7 mils (25 to 178 micrometers) thick and composed of room-temperature-vulcanizing (RTV) silicone. Specifies materials, equipment, spraying method, and quality requirements. Takes into account special needs of circuits made with complementary metal-oxide/semiconductor (CMOS) devices on circuit boards. Special attention given to preventing damage by electrostatic discharge, to which CMOS circuits especially sensitive.
The present invention provides electronically conducting polymer films formed from photosensitive formulations of pyrrole and an electron acceptor that have been selectively exposed to UV light, laser light, or electron beams. The formulations may include photoinitiators, flexibilizers, solvents and the like. These solutions can be used in applications including printed circuit boards and through-hole plating and enable direct metallization processes on non-conducting substrates. After forming the conductive polymer patterns, a printed wiring board can be formed by sensitizing the polymer with palladium and electrolytically depositing copper.
The present invention provides electronically conducting polymer films formed from photosensitive formulations of pyrrole and an electron acceptor that have been selectively exposed to UV light, laser light, or electron beams. The formulations may include photoinitiators, flexibilizers, solvents and the like. These solutions can be used in applications including printed circuit boards and through-hole plating and enable direct metallization processes on non-conducting substrates. After forming the conductive polymer patterns, a printed wiring board can be formed by sensitizing the polymer with palladium and electrolytically depositing copper.
Array of tiny probes tests complex printed circuit boards prior to mounting of microcircuit chips and other active and passive components. Insertion and alignment of board, performance of entire computer-controlled test, and printing of results requires about a minute; performed manually same tests require as much as 30 hours.
The goal of the project was to evaluate prototypes of an experimental thruster developed by the University of Arkansas (UA), Fayetteville, AR. The design under evaluation is a radio frequency (RF) electrostatic thruster that was fabricated using the low-temperature, co-fired ceramic (LTCC) materials and fabrication process. This materials system is analogous to printed circuit board (PCB) technology with the most significant difference being that the laminate is replaced by a ceramic material and the copper layer is replaced by printed sinterable silver paste. LTCC designs are baked after fabrication and assembled to realize an entirely monolithic structure with internal conductors, vias, and cavities. In this process, the LTCC electrostatic thruster (LTCC-ET) that is the subject of the present work becomes a monolithic ceramic thruster capable of withstanding temperatures in excess of 500 ºC. The UA and NASA Marshall Space Flight Center (MSFC) jointly performed prototype testing on the LTCC-ET under a NASA Cooperative Agreement Notice (CAN) award. The LTCC-ET was tested at MSFC in May 2018 over a 1-week period. There were two goals for the test program: (1) Testing to determine the operating parameters required to create plasma ignition in the test articles. This was explored by setting a propellant flowrate and increasing RF power until plasma ignition was observed. Testing was conducted with both argon and krypton. (2) Investigate the thrust and specific impulse (Isp) performance of the thruster as a function of propellant flowrate and grid voltage. This goal was not met during the project as technical challenges in maintaining stable plasma ignition arose due to stress and heating of the RF power feed. In summary, a prototype thruster design (consisting of three packaged units) was fabricated by UA and tested for the first time under vacuum conditions at MSFC to experimentally determine basic performance metrics and functionality. It was found that the design was not sufficiently optimized or robust enough in its initial iteration to support a significant test campaign or characterization program. It was concluded that the propellant outlet channels must be reduced in size with the flowpaths adjusted to increase propellant residence time in the thruster, and that the RF connector must be replaced with a version capable of handling higher power throughput and heating. However, even in its unoptimized form, a plasma could be produced in the LTCCET, demonstrating the efficacy of the design approach. The design is especially compelling due to its low cost to manufacture and, more importantly, its scalability of size and power throughput. Low cost and scalability are also important in that additional functionalities, such as thrust vectoring and plume charge neutralization, can be integrated into future designs with minimal additional cost. This project has matured the LTCC-ET development Technology Readiness Level (TRL) from 1 to 2. The low-cost RF plasma source portion of the LTCC device was matured from TRL 2 to 4 through the demonstration of RF plasma ignition under vacuum conditions.
Landslides are a global and frequent natural hazard, affecting many communities and infrastructure networks. Technological solutions are needed for long-term, large-scale condition monitoring of infrastructure earthworks or natural slopes. However, current instruments for slope stability monitoring are often costly, require a complex installation process and/or data processing schemes, or have poor resolution. Wireless sensor networks comprising low-power, low-cost sensors have been shown to be a crucial part of landslide early warning systems. Here, we present the development of a novel sensing approach that uses linear arrays of three-axis accelerometers for monitoring changes in sensor inclination, and thus the surrounding soil’s deformation. By combining these deformation measurements with depth-resolved temperature measurements, we can link our data to subsurface thermal–hydrological regimes where relevant. In this research, we present a configuration of cascaded I2C sensors that (i) have ultra-low power consumption and (ii) enable an adjustable probe length. From an electromechanical perspective, we developed a novel board-to-board connection method that enables narrow, semi-flexible sensor arrays and a streamlined assembly process. The low-cost connection method relies on a specific FR4 printed circuit board design that allows board-to-board press fitting without using electromechanical components or solder connections. The sensor assembly is placed in a thin, semi-flexible tube (inner diameter 6.35 mm) that is filled with an epoxy compound. The resulting sensor probe is connected to an AA-battery-powered data logger with wireless connectivity. We characterize the system’s electromechanical properties and investigate the accuracy of deformation measurements. Our experiments, performed with probes up to 1.8 m long, demonstrate long-term connector stability, as well as probe mechanical flexibility. Furthermore, our accuracy analysis indicates that deformation measurements can be performed with a 0.390 mm resolution and a 95% confidence interval of ±0.73 mm per meter of probe length. This research shows the suitability of low-cost accelerometer arrays for distributed soil stability monitoring. In comparison with emerging low-cost measurements of surface displacement, our approach provides depth-resolved deformation, which can inform about shallow sliding surfaces.
We have developed a series of compact RF mixing boards by integrating I/Q quadrature mixing, IF(intermediate frequency)/LO(local oscillator)/RF power level adjustments, and DC (direct current) bias fine tuning on a 40 mm × 80 mm 4-layer PCB (printed circuit board) board with EMI (electromagnetic interference) shielding.
Newly developed multilayer structures of well-known polymer insulation materials significantly improved dielectric breakdown voltage, VB, or dielectric strength, K, if well-bonded, when compared to those of single material insulations or the commercial SOA systems, such as Teflon-Kapton-Teflon (TKT), at the same overall thickness. To date, the greatest improvement of the new structures from a few candidate materials, including various types of Kapton PIs and PFA or PET as bond layer (BL), was about 61% higher than that of the Kapton PI alone films, 40.1 vs. 24.9 kV, which was translated to 86.3% decrease in insulation thickness, thus significant volume and weight reduction of the final system. However, it was of interest to note that most improvements of the multilayer structures occurred at thicker overall thicknesses, above ~ 0.15 mm. Extensive analyses also showed that K of the multilayer structures increased with (i) decreasing individual layer thickness regardless of material type, (ii) increasing total accumulated thickness of PI or overall PI/BL ratio, and (iii) increasing number of interface or total number of layers, but only above the aforementioned overall thickness limit. Increases in VB of the multilayer structures were directly correlated with damage evolution and failure mode. With further material-design-process optimizations of the multilayer structures, it was expected to achieve other multifunctionalities, such as high partial discharge (PD) resistance, improved durability, EMI shielding, and high thermal dissipation in addition to high dielectric strength. These new structures can be used in various high voltage and high temperature applications, such as future hybrid or all electric aircraft wiring and power transmission as well as many other non-aerospace high power cables, electronic parts and components, printed circuit board, and so forth. The multilayer insulation system can be easily processed and manufactured with various conductor types via calendaring, compression-molding, stamping, laminating, vacuum-bagging and autoclaving, or 3D printing, even for complex 3-D components. Based on their unique structural configurations and potential capabilities, the new insulation system was identified as micro-multilayer multifunctional electrical insulation (MMEI). Patent application of the MMEI concept and current design configurations was filed for a 1-year provisional application (OAI-58834, Serial No.: 62/659,234), pending conversion to a U.S. utility application. This paper presents details of the MMEI structures, their dielectric performance analyses, potential mechanisms, and commercial scaleup feasibility assessment.
Newly developed multilayer structures of well-known polymer insulation materials significantly improved dielectric breakdown voltage, VB, or dielectric strength, K, if well-bonded, when compared to those of single material insulations or the commercial SOA systems, such as Teflon-Kapton-Teflon (TKT), at the same overall thickness. To date, the greatest improvement of the new structures from a few candidate materials, including various types of Kapton PIs and PFA or PET as bond layer (BL), was about 61% higher than that of the Kapton PI alone films, 40.1 vs. 24.9 kV, which was translated to 86.3% decrease in insulation thickness, thus significant volume and weight reduction of the final system. However, it was of interest to note that most improvements of the multilayer structures occurred at thicker overall thicknesses, above ~ 0.15 mm. Extensive analyses also showed that K of the multilayer structures increased with (i) decreasing individual layer thickness regardless of material type, (ii) increasing total accumulated thickness of PI or overall PI/BL ratio, and (iii) increasing number of interface or total number of layers, but only above the aforementioned overall thickness limit. Increases in VB of the multilayer structures were directly correlated with damage evolution and failure mode. With further material-design-process optimizations of the multilayer structures, it was expected to achieve other multifunctionalities, such as high partial discharge (PD) resistance, improved durability, EMI shielding, and high thermal dissipation in addition to high dielectric strength. These new structures can be used in various high voltage and high temperature applications, such as future hybrid or all electric aircraft wiring and power transmission as well as many other non-aerospace high power cables, electronic parts and components, printed circuit board, and so forth. The multilayer insulation system can be easily processed and manufactured with various conductor types via calendaring, compression-molding, stamping, laminating, vacuum-bagging and autoclaving, or 3D printing, even for complex 3-D components. Based on their unique structural configurations and potential capabilities, the new insulation system was identified as micro-multilayer multifunctional electrical insulation (MMEI). Patent application of the MMEI concept and current design configurations was filed for a 1-year provisional application (OAI-58834, Serial No.: 62/659,234), pending conversion to a U.S. utility application. This paper presents details of the MMEI structures, their dielectric performance analyses, potential mechanisms, and commercial scaleup feasibility assessment.
An emerging trend in advanced manufacturing is printed electronics and sensors. The ability to print customized electronics and sensors integrated into functional packages is a growing need within a variety of growing markets such as smart manufacturing, internet of things (IoT), and the small satellite industry. Both Oak Ridge National Laboratory (ORNL) and the MITRE Corporation have seedling research efforts evaluating the potential for future printed electronic systems. High frequency, wide-bandwidth phased array antennas (i.e. >45 GHz) open the door to new applications. However, such sensors require currently prohibitively small feature sizes for commercial 3D printing technologies along with increasing challenges with connecting the driving electronics to such features. An additional finding with related advanced manufacturing challenges is the rapid production of 3D additive connectors for integration with commercial printed circuit boards (PCBs), primarily for advanced in-circuit inspection techniques. This work is developing additive manufacturing processes for producing connected and conductive fine scale 3D features. The primary focus was on aerosol-jet printing (AJP), which has a small minimum resolution (<50 µm) but is traditionally printed flat with small height/width aspect ratios <<1, and developing controls to enable fully 3D, high aspect ratio, and unsupported features. In Phase 1 of this effort, baselines of process performance were characterized, and test coupons produced for both ultra-high frequency antennas and microstructures to support reverse engineering of PCBs. In Phase 2, these efforts will be extended for system demonstration of ultra-high frequency antenna arrays, as well as reverse engineering circuitry for dense PCBs.
Metallo-organic ink containing silver (with some bismuth as adhesion agent) applied to printed-circuit boards and pyrolized in air to form electrically conductive patterns. Ink contains no particles of silver, does not have to be mixed during use to maintain homogeneity, and applied to boards by ink-jet printing heads. Consists of silver neodecanoate and bismuth 2-ethylhexanoate dissolved in xylene and/or toluene.
The objectives are to demonstrate how the microstructure of materials may be revealed by abrasive polishing and chemical etching, and to illustrate how microstructural information is used to monitor manufacturing processes, provide in-depth inspection, and perform failure analysis. Microstructural analysis is the procedure used to reveal the internal microstructural details of a material or part by sectioning and polishing the cut surface so that it may be examined under a suitable microscope. A printed wiring board was selected as the test material because it contains both metals and nonmetals that have distinctive microstructures, and because this technique is used throughout the electronic industry as a key quality control tool. The three principle component materials in printed circuit boards are glass/epoxy laminates faced with copper foil; copper, deposited by both electroless and electrolytic plating; and tin/lead solder. Sample preparation, mounting, grinding, polishing, and examination and analysis are discussed.
Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.
The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design
Microwave connectors with a planar geometry have been demonstrated using additive manufacturing techniques. This planar form factor is expected to enable connectors to be integrated directly with other components onto a printed circuit board. The connectors were developed with multiple signal lines that will increase the density of signal connections to PCBs, eliminating the physical constraints of single-signal COTS microwave connectors. This work developed electromagnetic models (using Ansys HFSS) of these planar connectors to predict performance and optimize connector design. Materials and printing processes were developed to fabricate the connectors based on high-temperature PEEK thermoplastics. The multiple signal connectors were designed to operate over the 1-6GHz band and are built upon the single signal printed planar geometry connector introduced in a previous paper [1].