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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Detector circuit accurately separates and counts phase-shift pulses over wide range of basic pulse-rate frequency, and also provides reasonable representation of full repetitive EKG waveform. Single telemeter implanted in small animal monitors not only body temperature but also animal movement and heart rate.
A starter circuit particularly suitable for a plasma of an ion engine for a spacecraft includes a power supply having an output inductor with a tap. A switch is coupled to the tap. The switch has a control input. A pulse control logic circuit is coupled to said control input, said pulse control logic circuit controlling said switch to an off state to generate a high voltage discharge.
A starter circuit particularly suitable for a plasma of an ion engine for a spacecraft includes a power supply having an output inductor with a tap. A switch is coupled to the tap. The switch has a control input. A pulse control logic circuit is coupled to said control input, said pulse control logic circuit controlling said switch to an off state to generate a high voltage discharge.
Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.
The invention is a method and circuit for controlling the evolution time interval of a laser output pulse used for making precise spectral measurements. It comprises the means for pumping a laser medium in a resonator that includes a Q-switch and polarizer that act in combination to control the loss in the resonator. A photodiode senses the resulting fluorescence which is applied to a two level Q-switch and polarizer from high to intermediate to substantially zero loss states to control the evolution time interval of the resulting laser output pulse.
Oscillator circuit needing no standby power and pulsed on when required, with application to tone generators
A compact electronic circuit was developed to detect prelasing in Q-swithed pulsed laser systems and once detected to shut down the laser before the next laser pulse occurs. The circuit is small, compact, and uses a minimum of components which makes it quite economical, thus readily lending itself to commercial applications. It can easily be incorporated into virtually any Q-switched laser system or reliability of a laser system by reducing a source of possible costly optical damage. The circuit operation and instrument requirements necessary to incorporate the circuit into a laser system are discussed.
Analog-to-digital converter-pulse height analyzer for data reduction from balloon measurements
The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.
Abstract not provided.
Abstract not provided.
The U.S. Army Research Laboratory, Fort Monmouth, NJ, has developed and is installing two 3.3 MW high speed solid state circuit breakers at the Army's Pulse Power Center. These circuit breakers will interrupt 4160V three phase power mains in no more than 300 microseconds, two orders of magnitude faster than conventional mechanical contact type circuit breakers. These circuit breakers utilize Gate Turnoff Thyristors (GTO's) and are currently utility type devices using air cooling in an air conditioned enclosure. Future refinements include liquid cooling, either water or two phase organic coolant, and more advanced semiconductors. Each of these refinements promises a more compact, more reliable unit.
Capacitive integrator circuit using Silicon Controlled Switches /SCS/ insures output voltage linearly proportional to input pulse width. This circuit provides high input impedance and relatively low output impedance.
Design and manufacture of direct current torquer amplifier with pulse width modulation circuit
A simple Pulse Overlay (PO) circuit using a logic OR gate was developed to overlay a precise leading edge 1 Pulse Per Second (1PPS) time reference marker from a GPS receiver onto a Non-Return -to- Zero-Level (NRZ-L) Pulse Code Modulation (PCM) telemetry data stream to validate time stamp accuracy and measure propagation delay (PD) in telemetry equipment.
The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.
Transformer-coupled output stage is used with pulse-width modulated class-D dc amplifiers. Circuit is comprised of two channels corresponding to negative and positive input signals. Amplitude of secondary-current triangular pulse is function of duration of driving pulse. Therefore, circuit converts pulse-width modulated driving signal to pulse-amplitude modulated signal.
The analytical design of the feedback circuit for a d-c flyback converter requires the formulation of a model defining the static and dynamic performance of the forward loop. This paper describes the steps which were taken to develop a linear continuous model of a typical flyback circuit. Although the method uses several approximations to simplify the work, the resulting model was found to duplicate the performance of the actual circuit very closely. The model makes it possible to design the feedback circuit using well known linear feedback techniques. The method is an extension of prior work in the modeling of pulse-width controlled circuits.