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A light-activated semiconductor device usable as an optoelectronic switch, pulse generator or optical detector is provided. A semiconductor device is disclosed which provides back-to-back metal-thin oxide-silicon (MTOS) capacitors. Each capacitor includes a thin, light-absorptive aluminum electrode which overlies a thin oxide layer and a lightly doped region implanted in an intrinsic silicon substrate.
The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. Silicon carbide's demonstrated ability to function under extreme high-temperature, high power, and/or high-radiation conditions will enable significant improvements to a far ranging variety of applications and systems. These improvements range from improved high-voltage switching for energy savings in public electric power distribution and electric vehicles, to more powerful microwave electronics for radar and cellular communications, to sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. In the case of jet engines, uncooled operation of 300 to 600 C SiC power actuator electronics mounted in key high-temperature areas would greatly enhance system performance and reliability. Because silicon cannot function at these elevated temperatures, the semiconductor device circuit components must be made of SiC. Lewis' HTIES group recently fabricated and characterized high-temperature SiC rectifier diodes whose record-breaking characteristics represent significant progress toward the realization of advanced high-temperature actuator control circuits. The first figure illustrates the 600 C probe-testing of a Lewis SiC pn-junction rectifier diode sitting on top of a glowing red-hot heating element. The second figure shows the current-versus voltage rectifying characteristics recorded at 600 C. At this high temperature, the diodes were able to "turn-on" to conduct 4 A of current when forward biased, and yet block the flow of current ($quot;turn-off") when reverse biases as high as 150 V were applied. This device represents a new record for semiconductor device operation, in that no previous semiconductor electronic device has ever simultaneously demonstrated 600 C functionality, and 4-A turn-on and 150-V rectification. The high operating current was achieved despite severe device size limitations imposed by present-day SiC wafer defect densities. Further substantial increases in device performance can be expected when SiC wafer defect densities decrease as SiC wafer production technology matures.
Wideband wattmeter for measurement and analysis of power dissipation in semiconductor switching devices, considering occurrence of peaks, frequency dependency of average dissipation, etc
A semiconductor device has one surface of P type conductivity material having a wide energy bandgap and a large crystal lattice parameter. Applied to the P type surface of the semiconductor device is a degenerate region of semiconductor material, preferably a group III-V semiconductor material, having a narrower energy bandgap. The degenerate region is doped with tin to increase the crystal lattice of the region to more closely approximate the crystal lattice of the one surface of the semiconductor device. The degenerate region is compensatingly doped with a P type conductivity modifier. An electrical contact is applied to one surface of the degenerate region forming an ohmic contact with the semiconductor device.
Conduction mechanisms and transient behavior of memory device using semiconductor devices
A method of effecting modifications at the surfaces of materials using low energy ion beams of known quantum state, purity, flux, and energy is presented. The ion beam is obtained by bombarding ion-generating molecules with electrons which are also at low energy. The electrons used to bombard the ion generating molecules are separated from the ions thus obtained and the ion beam is directed at the material surface to be modified. Depending on the type of ion generating molecules used, different ions can be obtained for different types of surface modifications such as oxidation and diamond film formation. One area of application is in the manufacture of semiconductor devices from semiconductor wafers.
A ceramic- and thick-film-materials-based prototype electronic package designed for silicon carbide (SiC) high-temperature sensors and electronics has been successfully tested at 500 C in an oxygen-containing air environment for 500 hours. This package was designed, fabricated, assembled, and electronically evaluated at the NASA Glenn Research Center at Lewis Field with an in-house-fabricated SiC semiconductor test chip. High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as space missions to the inner solar system or the emission control electronics and sensors in aeronautical engines. Single-crystal SiC has such excellent physical and chemical material properties that SiC-based semiconductor electronics can operate at temperatures over 600 C, which is significantly higher than the limit for Si-based semiconductor devices. SiC semiconductor chips were recently demonstrated to be operable at temperatures as high as 600 C, but only in the probe station environment because suitable packaging technology for sensors and electronics at temperatures of 500 C and beyond did not exist. Thus, packaging technology for SiC-based sensors and electronics is immediately needed for both application and commercialization of high-temperature SiC sensors and electronics. In response to this need, researchers at Glenn designed, fabricated, and assembled a prototype electronic package for high-temperature electronics, sensors, and microelectromechanical systems (MEMS) using aluminum nitride (AlN) substrate and gold (Au) thick-film materials. This prototype package successfully survived a soak test at 500 C in air for 500 hours. Packaging components tested included thick-film high-temperature metallization, internal wire bonds, external lead bonds, and a SiC diode chip die-attachment. Each test loop, which was composed of thick-film printed wire, wire bond, and lead bond was subjected to a 50-mA direct current for 250 hours at 500 C.
We study recently reported drain current Id-drain voltage Vd characteristics of a carbon nanotube metal semiconductor diode device with the gate voltage Vg applied to modulate the carrier density in the nanotube. The diode was kink-shaped at the metal-semiconductor interface. It was shown that (1) larger negative Vg blocked Id more effectively in the negative Vd region, resulting in the rectifying Id-Vd characteristics, and that (2) positive Vg allowed Id in the both Vd polarities, resulting in the non-rectifying characteristics. The negative Vd was the Schottky reverse direction, judging from the negligible Id behavior for a wide region of -4 V less than Vd less than 0 V, with Vg = -4 V. Such negative Vg would attract positive charges from the metallic electrodes (charge reservoir) to the nanotube and lower the nanotube Fermi energy (EF). With larger negative Vg, the experiment showed that the Schottky forward direction (Vd greater than 0) had a smaller turn-on voltage and the Schottky reverse direction (Vd less than 0) was more resistant to the tunneling breakdown. Therefore, the majority carriers in the transport would be electrons since they can see a lower tunneling barrier (shallower built-in potential) in the forward direction when EF is lowered, and a thicker tunneling barrier (Schottky barrier) in the reverse direction due to the reduction in the electron density when EF is lowered.
Improving radiation resistance of silicon semiconductor junctions by doping with lithium
We study recently reported drain current I(sub d)-drain voltage V(sub d) characteristics of a carbon nanotube metal-semiconductor diode device with the gate voltage V(sub g) applied to modulate the carrier density in the nanotube. The diode was kink-shaped at the metal-semiconductor interface. It was shown that (1) larger negative V(sub g) blocked I(sub d) more effectively in the negative V(sub d) region, resulting in the rectifying I(sub d)-V(sub d) characteristics, and that (2) positive V(sub g) allowed I(sub d) in the both V(sub d) polarities, resulting in the non-rectifying characteristics. The negative V(sub d) was the Schottky reverse direction, judging from the negligible I(sub d) behavior for a wide region of -4 V (is less than) V(sub d) (is less than) 0 V, with V(sub g) = -4 V. Such negative V(sub g) would attract positive charges from the metallic electrodes (charge reservoir) to the nanotube and lower the nanotube Fermi energy (E(sub F)). With larger negative V(sub g), the experiment showed that the Schottky forward direction (V(sub d) (is greater than) 0) had a smaller turn-on voltage and the Schottky reverse direction (V(sub d) (is less than) 0) was more resistant to the tunneling breakdown. Therefore, the majority carriers in the transport would be electrons since they can see a lower tunneling barrier (shallower built-in potential) in the forward direction when E(sub F) is lowered, and a thicker tunneling barrier (Schottky barrier) in the reverse direction due to the reduction in the electron density when E(sub F) is lowered.
A body of semiconductor material having a first surface and a second surface spaced from the first surface includes a first layer along the first surface, a second layer along the second surface, a third layer between and contiguous to the first and second layers. The third layer is of a conductivity type opposite that of the first and second layers so as to form first and second P-N junctions respectively therebetween. The thickness of the third layer is at least twice the minority carrier diffusion length of the semiconductor material, so that carriers generated within the third layer have a high probability of being collected by one of the P-N junctions. The body includes means for electrically connecting the first and second P-N junctions and means for transferring the carriers collected at the first P-N junction to a portion of the first surface.
The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.
Electrical and electronic semiconductor device failures from metallurgical viewpoint
Report describes effects of power and temperature overstress on Semtech and Micro Semiconductor devices. Only two Semtech diodes failed catastrophically. Testing on Micro Semiconductor devices stopped because failure limit was reached. Micro diodes suffered lead separation.
Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.
Due to memory limitations, iterative methods have become the method of choice for large scale semiconductor device simulation. However, it is well known that these methods still suffer from reliability problems. The linear systems which appear in numerical simulation of semiconductor devices are notoriously ill-conditioned. In order to produce robust algorithms for practical problems, careful attention must be given to many implementation issues. This paper concentrates on strategies for developing robust preconditioners. In addition, effective data structures and convergence check issues are also discussed. These algorithms are compared with a standard direct sparse matrix solver on a variety of problems.
Report describes effects of power and temperature overstress on Texas Instruments and National Semiconductor devices. Texas Instruments devices had only two failures in 2500 hours of testing. National Semiconductor devices reached 50% failure limit. No consistent failure mode was detected.
The Voyager spacecraft is subject to radiation from external natural space, from radioisotope thermoelectric generators and heater units, and from the internal environment where penetrating electrons generate surface ionization effects in semiconductor devices. Methods for radiation hardening and tests for radiation sensitivity are described. Results of characterization testing and sample screening of over 200 semiconductor devices in a radiation environment are summarized.