Search NASA⌕ Search

SEARCH · Search NASA

Results for “SEMICONDUCTOR DEVICE”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2012

Radiation protection for high energy implantation of light ions in a production environment

In recent years the irradiation of semiconductor devices by light ions with high energies has increasingly become a well-established method to adjust charge carrier lifetimes in semiconductor devices. To introduce this process into the end of frontend production environment several measures in terms of radiation safety will have to be obeyed. An overview on thresholds for particles induced gamma emission will be given, starting with the {sup 11}B(p,{gamma}){sup 12}C reaction at 163keV. The environment has to be shielded from gamma rays, therefore those implanters have to be situated in adequate enclosures. Calculations for specific implant energies are done to define the thicknesses of tool enclosures. A set of radiation detectors monitors the values at well-defined positions online and radiation values are fed into a superordinate system that is directly coupled to the main power supply of the implanter.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Gallium Oxide Heterojunction Diodes for 400 °C High‐Temperature Applications

β ‐Ga 2 O 3 ‐based semiconductor devices are expected to have significantly improved high‐power and high‐temperature performance due to its ultrawide bandgap of close to 5 eV. However, the high‐temperature operation of these ultrawide‐bandgap devices is usually limited by the relatively low 1–2 eV built‐in potential at the Schottky barrier with most high‐work‐function metals. Herein, heterojunction p ‐NiO/n‐ β ‐Ga 2 O 3 diodes fabrication and optimization for high‐temperature device applications are reported, demonstrating a current rectification ratio ( I ON / I OFF ) of more than 10 6 at 410 °C. The NiO heterojunction diode can achieve higher turn‐on ( V ON ) voltage and lower reverse leakage current compared to the Ni‐based Schottky diode fabricated on the same single‐crystal β ‐Ga 2 O 3 substrate, despite charge transport dominated by interfacial recombination. Electrical characterization and device modeling show that these advantages are due to a higher built‐in potential and additional band offset. These results suggest that heterojunction p–n diodes based on β ‐Ga 2 O 3 can significantly improve high‐temperature electronic device and sensor performance.

Sohel, Shahadat H.↗
DOE OSTI2019

Controller-Hardware-in-the-Loop Test Bed for Fast-Switching SiC-Based 50-kW PV Inverter

The recent advent of wideband gap power semiconductor devices will lay the path to the future power converters. These devices provide the advantage of high switching speed and lower losses. The high cost and high switching speeds of these devices provide a challenge in the development and validation of the fast switching inverter controls with accuracy of that of a hardware setup. In this paper an FPGA real-time simulator-based controller-hardware-in-the-loop (CHIL) testbed is used to verify the low-level and advanced inverter controls fast switching wide bandgap-based string photovoltaic inverter. The paper also includes development of the CHIL testbed, which is run at a time-step of 500 ns in order to implement 20 kHz switching frequency. The developed CHIL testbed is validated through experimental results from a three-phase, 50 kW, 480 VLLrms SiC devices based inverter.

14 SOLAR ENERGY↗
DOE OSTI2014

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

Low-temperature (≤200 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-enhanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems not only from the growth conditions but also from unintentional contamination of the reactor. Based on our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2013

Development of molecular beam epitaxy technology for III–V compound semiconductor heterostructure devices

Molecular beam epitaxy (MBE) is a versatile ultrahigh vacuum technique for growing multiple epitaxial layers of semiconductor crystals with high precision. The extreme control of the MBE technique over composition variation, interface sharpness, impurity doping profiles, and epitaxial layer thickness to the atomic level makes it possible to demonstrate a wide variety of novel semiconductor structures. Since its invention nearly 40 years ago, the MBE technique has evolved from a laboratory apparatus for exploring new materials and novel devices to a favored tool for the mass production of III–V high-speed devices. This paper will review some of the past developments in this technology and propose an outlook of future developments.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Thermal Management for Planar Package Power Electronics (CRADA Final Report)

The National Renewable Energy Laboratory (NREL) and John Deere Electronic Solutions (JDES) collaborated to develop and evaluate computer models and simulations related to the thermal performance of semiconductor device packaging for an inverter of an off-road vehicle ("Semiconductor Packaging"). The objective of the research was for NREL and JDES to develop a two or three-dimensional computer-aided design model of the Semiconductor Packaging ("Computer Model") for thermal performance evaluation in a simulation. The project developed computer models of a Semiconductor Package of silicon-carbide semiconductor devices with appropriate thermal dissipation via one or more of the following thermal features: a double-sided planar cooling configuration, an air-cooled configuration, a liquid-cooled configuration for off-road inverter applications in a relevant simulated operating environment. It is noted that surface area and prototype product embodiment consisting of air-cooled and liquid-cooled configurations may and may not be in direct contact with power semiconductor chips. The idea was to explore and develop packaging and thermal management technology for power semiconductors that was most effective in the performance yet had least burden in overall product cost for a given application.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2024

N-type molecular doping of a semicrystalline conjugated polymer through cation exchange

Control of electrical doping is indispensable in any semiconductor device, and both efficient hole and electron doping are required for many devices. In organic semiconductors, however, electron doping has been essentially more problematic compared to hole doping because in general organic semiconductors have low electron affinities and require dopants with low ionization potentials that are often air-sensitive. Here, we adapt an efficient molecular doping method, so-called ion-exchange doping, to dope electrons in a polymeric semiconductor. We initially reduce the polymeric semiconductor using one electron transfer from molecular dopants, and then the ionized dopants in the resulting air-unstable films are replaced with secondary ions via cation exchange. Improved ambient stability and crystallinity of the doped polymeric semiconductors are achieved when a specific bulky molecular cation was chosen as the secondary ion, compared to conventional methods. The presented strategy can overcome the trade-off relationship between reducing capability and ambient stability in molecular dopants, and a wider selection of dopant ions will help to realize ambient-stable electron conductors.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Evaluation of Converter Performance Considering Static and Dynamic Device Part-to-Part Variability

This paper presents a methodology to incorporate and analyze the impact of semiconductor device part-to-part variation on power converter performance. By integrating extensive static and dynamic device characterization data with an automated compact model generation process that reflects manufacturing variability, device models with inherent variability features are utilized in converter simulations for a comprehensive assessment of performance impacts. The traditional converter performance evaluation process typically yields fixed efficiency values, often dismissing the inherent part-to-part variability caused by the manufacturing process of semiconductor devices. To address this limitation, a large population of devices was characterized to capture variations in static parameters-such as transfer, output, and capacitance characteristics-as well as dynamic behaviors, including switching losses. This data-driven approach enables the development of individual compact models, which were then integrated into converter simulations to evaluate efficiency ranges rather than single point estimated values. The converter simulation results show that part-to-part component variation can lead to significant efficiency deviations, exceeding several percentage points in high-power conversion applications. By offering a more accurate representation of converter behavior under real-world manufacturing conditions, this methodology enables designers to anticipate performance variability, improving the robustness of power converter designs.

device characterization↗
DOE OSTI2015

Strategies for Wide Bandgap, Inexpensive Transistors for Controlling High-efficiency Systems

Wide bandgap power semiconductor devices offer enormous energy efficiency gains in a wide range of potential applications. However, today, they remain too costly relative to Si devices to gain ubiquitous adoption in many higher power applications. In 2014, ARPA-E launched a new research program entitled SWITCHES, that seeks to enable the development of high voltage (1200 V+), high current (100 A) single die power semiconductor devices that, upon ultimately reaching scale, have the potential to reach functional cost parity ($/A) with silicon power transistors while also offering breakthrough relative circuit performance (low losses, high switching frequencies, and high temperature operation).

36 MATERIALS SCIENCE↗
DOE OSTI2026

PowerAmerica (Final Technical Report)

The U.S. Department of Energy’s Advanced Manufacturing Office (predecessor to AMMTO) established PowerAmerica in December 2014 to develop and accelerate the adoption of wide bandgap (WBG) semiconductor chips and power electronics in manufacturing. The objective was to spark early commercialization of energy efficient products; educate and train the workforce; create high-tech jobs; and nurture the growth of the U.S. WBG semiconductor manufacturing industry. PowerAmerica isled by North Carolina State University by way of a five-year, $140M cooperative agreement with DoE. This private-public partnership with DoE includes member companies ranging from startups and small-medium enterprises to large system integrators, world-class universities, and national labs. The WBG power electronic ecosystem formed by our diverse membership is focused on using advanced manufacturing to 1) lower the cost of silicon carbide and gallium nitride semiconductor devices to be comparable to silicon devices; 2) demonstrate the system benefits and energy efficiency advantages of WBG semiconductor power electronics through system demonstrations that validate their effectiveness; and 3) build an education pipeline for a skilled workforce to meet the future demand for emerging WBG semiconductor markets — and enhance U.S. economic competitiveness globally. PowerAmerica was initially funded in six budget periods, each lasting 12 to 18 months. By the end of Budget Period 6 (August 2023), PowerAmerica had achieved its major objectives in technology development, semiconductor device cost reduction, ecosystem growth and engagement, and education and workforce development. Through strategic foundry investments, we helped to establish the first U.S. SiC foundry (X-FAB) and supported a lab (Microchip) to start SiC volume production. We’ve helped bring together companies from different parts of the supply chain, resulting in several successful new partnerships and business relationships. Through projects with some of the largest manufacturers of energy-intensive equipment in the U.S. — John Deere, GE, United Technologies, Raytheon, Carrier, Toshiba, and others — we have successfully demonstrated the energy and system benefits of WBG technology. We have also harnessed the unique capabilities and facilities of national labs — the Naval Research Laboratory, National Renewable Energy Laboratory, and Argonne National Laboratory — to help solve challenging technical problems for industry. Thanks to our many webinars, tutorials, annual events, and presence at major energy and electronics conferences around the world, the PowerAmerica name has become synonymous with WBG technology advancement. The commercial interest in WBG technology is higher than ever; companies and governments around the world have announced hundreds of millions of dollarsin future investment to build capacity — and compete with silicon in many markets and applications. We have trained hundreds of engineering students, from universities across the U.S., through hands-on projects and WBG coursework. Working professionals have also benefited through the years from our many targeted short courses, tutorials, and technical webinars. In short, PowerAmerica has made great strides in each of our key objectives, and the organization has been operating without government or NC State

14 SOLAR ENERGY↗
DOE OSTI2016

Diode having trenches in a semiconductor region

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

Low temperature recovery of OFF-state stress induced degradation of AlGaN/GaN high electron mobility transistors

Thermal annealing is a widely used strategy to enhance semiconductor device performance. However, the process is complex for multi-material multi-layered semiconductor devices, where thermoelastic stresses from lattice constant and thermal expansion coefficient mismatch may create more defects than those annealed. We propose an alternate low temperature annealing technique, which utilizes the electron wind force (EWF) induced by small duty cycle high density pulsed current. To demonstrate its effectiveness, we intentionally degrade AlGaN/GaN high electron mobility transistors (HEMTs) with accelerated OFF-state stressing to increase ON-resistance ∼182.08% and reduce drain saturation current ∼85.82% of pristine condition at a gate voltage of 0 V. We then performed the EWF annealing to recover the corresponding values back to ∼122.21% and ∼93.10%, respectively. The peak transconductance, degraded to ∼76.58% of pristine at the drain voltage of 3 V, was also recovered back to ∼92.38%. This recovery of previously degraded transport properties is attributed to approximately 80% recovery of carrier mobility, which occurs during EWF annealing. We performed synchrotron differential aperture x-ray microscopy measurements to correlate these annealing effects with the lattice structural changes. We found a reduction of lattice plane spacing of (001) planes and stress within the GaN layer under the gate region after EWF annealing, suggesting a corresponding decrease in defect density. Application of this low-temperature annealing technique for in-operando recovery of degraded electronic devices is discussed.

Physics↗
DOE OSTI2014

Atomic scale study of polar Lomer–Cottrell and Hirth lock dislocation cores in CdTe

Dislocation cores have long dominated the electronic and optical behaviors of semiconductor devices and detailed atomic characterization is required to further explore their effects. Miniaturization of semiconductor devices to nanometre scale also puts emphasis on a material's mechanical properties to withstand failure due to processing or operational stresses. Sessile junctions of dislocations provide barriers to propagation of mobile dislocations and may lead to work-hardening. The sessile Lomer–Cottrell and Hirth lock dislocations, two stable lowest elastic energy stair-rods, are studied in this paper. More specifically, using atomic resolution high-angle annular dark-field imaging and atomic-column-resolved X-ray spectrum imaging in an aberration-corrected scanning transmission electron microscope, dislocation core structures are examined in zinc-blende CdTe. A procedure is outlined for atomic scale analysis of dislocation junctions which allows determination of their identity with specially tailored Burgers circuits and also formation mechanisms of the polar core structures based on Thompson's tetrahedron adapted to reactions of polar dislocations as they appear in CdTe and other zinc-blende solids. Strain fields associated with the dislocations calculated via geometric phase analysis are found to be diffuse and free of `hot spots' that reflect compact structures and low elastic energy of the pure-edge stair-rods.

CdTe↗
DOE OSTI2021

Role of Decomposition Product Ions in Hysteretic Behavior of Metal Halide Perovskite

Ion migration is one of the most debated mechanisms and credited with multiple observed phenomena and performance in metal halide perovskites (MHPs) semiconductor devices. However, to date, the migration of ions and their effects on MHPs are not still fully understood, largely due to a lack of direct observations of temporal ion migration. In this work, using direct observation of ion migration in-operando, we observe the hysteretic migration behavior of intrinsic ions (i.e., CH 3 NH 3 + and I – ) as well as reveal the migration behavior of CH 3 NH 3 + decomposition ions. We find that CH 3 NH 3 + decomposition products can be affected by light and accumulate at the interfaces under bias. These MHP decomposition products are tightly related to the device performance and stability. Complementary results of time-resolved Kelvin probe force microscopy (tr-KPFM) demonstrate a correlation between dynamics of these interfacial ions and charge carriers. Overall, we find that there are a number of mobile ions including CH 3 NH 3 + decomposition products in MHPs that need to be taken into account when measuring MHP device responses (e.g., charge dynamics) and should be considered in future optimization studies of MHP semiconductor devices.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2015

Enhanced electrical activation in In-implanted Ge by C co-doping

At high dopant concentrations in Ge, electrically activating all implanted dopants is a major obstacle in the fulfillment of high-performance Ge-channel complementary metal oxide semiconductor devices. In this letter, we demonstrate a significant increase in the electrically-active dopant fraction in In-implanted Ge by co-doping with the isovalent element C. Electrical measurements have been correlated with x-ray absorption spectroscopy and transmission electron microscopy results in addition to density functional theory simulations. With C + In co-doping, the electrically active fraction was doubled and tripled at In concentrations of 0.2 and 0.7 at. %, respectively. This marked improvement was the result of C-In pair formation such that In-induced strain in the Ge lattice was reduced while the precipitation of In and the formation of In-V clusters were both suppressed.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2020

Directly Linking Low-Angle Grain Boundary Misorientation to Device Functionality for GaAs Grown on Flexible Metal Substrates

A new growth method to make highly oriented GaAs thin films on flexible metal substrates has been developed, enabling roll-to-roll manufacturing of flexible semiconductor devices. The grains are oriented in the <001> direction with <1 degree misorientations between them, and they have a comparable mobility to single-crystalline GaAs at high doping concentrations. At the moment, the role of low-angle grain boundaries (LAGBs) on device performance is unknown. A series of electron backscatter diffraction (EBSD) and cathodoluminesence (CL) studies reveal that increased doping concentrations decrease the grain size and increase the LAGB misorientation. Cross-sectional scanning transmission electron microscopy (STEM) reveals the complex dislocation structures within LAGBs. Most importantly, a correlative EBSD/electron beam-induced current (EBIC) experiment reveals that LAGBs are carrier recombination centers and that the magnitude of recombination is dependent on the degree of misorientation. The presented results directly link increased LAGB misorientation to degraded device performance, and therefore, strategies to reduce LAGB misorientations and densities would improve highly oriented semiconductor devices.

36 MATERIALS SCIENCE↗
DOE OSTI2013

An atomic force microscopy-based method for line edge roughness measurement

With the constant decrease of semiconductor device dimensions, line edge roughness (LER) becomes one of the most important sources of device variability and needs to be controlled below 2 nm for the future technological nodes of the semiconductor roadmap. LER control at the nanometer scale requires accurate measurements. We introduce a technique for LER measurement based upon the atomic force microscope (AFM). In this technique, the sample is tilted at about 45 Degree-Sign and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The small radius of curvature of the tip together with the low noise level of a laboratory AFM result in high resolution images. Half profiles and LER values on all the height of the sidewalls are extracted from the 3D images using a procedure that we developed. The influence of sample angle variations on the measurements is shown to be small. The technique is applied to the study of a full pattern transfer into a simplified gate stack. The images obtained are qualitatively consistent with cross-section scanning electron microscopy images and the average LER values agree with that obtained by critical dimension scanning electron microscopy. In addition to its high resolution, this technique presents several advantages such as the ability to image the foot of photoresist lines, complex multi-layer stacks regardless of the materials, and deep re-entrant profiles.

36 MATERIALS SCIENCE↗