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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

Optical flip-flops and sequential logic circuits using a liquid crystal light valve

This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.

Fatehi, M. T.↗
NASA NTRS1986

Digital Pseudonoise Generator

Architecture developed for noise generator based on pseudorandom number sequence. Concept involves no additions or multiplications; outputs of set of feedback shift registers combined, bit-by-bit, in accordance with desired probability distribution. Digital, pseudorandom number output fed to digital-to-analog converter to generate pseudonoise signal suitable for testing broadband amplifiers.

Knoebel, A.↗
NASA NTRS1985

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗
NASA NTRS1985

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated in this study, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗
NASA NTRS1986

Frequency domain laser velocimeter signal processor

The features and performance parameters of the frequency domain laser velocimeter signal processor (FDSP) for examining flow phenomena are described. A candidate for replacing the standard signal processor, the FDSP can function receiving bursts of as few as 150 photons in an instantaneous mode or down to a photon resolved regime for an averaging mode. the FDSP has a nonlinear A/D converter and data storage shift registers (high speed recorder group), an elliptic digital filter bank, a controlling microprocessor and frequency and signal gain control circuits (low speed data processing group). The high speed group amplifies, digitizes, identifies and stores burst waveforms and the low speed group identifies the signal frequency within the burst after the signal passes through digital filters. The FDSP can operate in a near-autonomous mode using photon correlation techniques and requires no human intervention for calibration.

Meyers, J. F.↗
NASA NTRS1986

Single frequency multitransmitter telemetry

The invention relates to a single frequency multitransmitter telemetry system that will deliver a substantial amount of data at low cost. The invention consists essentially of a plurality of sensor transmitter units at different locations, with individual signal conditioning and logic, which send sampled data signals to a single receiver. The transmitters operate independently on the same frequency in a frequency shift keying modulation system and are not synchronized to the receiver. The problem of reception of data from more than one transmitter simultaneously is solved by discarding the data - when there is overlap of data from two or more transmitters, the data is discarded and when there is no overlap the data is retained. The invention utilizes a unique overlap detection technique to determine if data should be retained or discarded. When data is received from a transmitter, it goes into a shift register.

Carreno, Victor A.↗
NASA NTRS1988

Electronic Neural-Network Simulator

Experimental circuits faster than simulation programs run on digital computers. Serial shift register routes clock pulses C1 to neurons in sequence. Clock pulses C2 interrogate neurons. Neuron interconnection information stored in simulated synapses. Can be expanded to greater complexity.

Moopenn, Alex W.↗
NASA NTRS1989

Fast Asynchronous Data Communication Via Fiber Optics

Transmitter and receiver devised for asynchronous digital communication via optical fiber at rates above 100 Mb/s. Transmitter converts parallel data to serial for high-speed transmission; receiver recovers clock signal and converts data back to parallel. No phase-lock loops used. New receiver design avoids over-sampling altogether. Local sampling oscillator operating nominally at clock frequency generates N clock signals of equally spaced phase, used to clock incoming data into N separate shift registers.

Bergman, Larry A.↗
NASA NTRS1990

VLSI Reed-Solomon Encoder With Interleaver

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek↗
NASA NTRS1990

A bit-serial VLSI array processing chip for image processing

An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to mask PEs individually. A modified grid interconnection scheme allows each PE to communicate with each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1-micron CMOS design contains over 1.1 x 10 to the 6th transistors on an 11.0 x 11.7-mm die.

Heaton, Robert↗
NASA NTRS1989

Systolic array processing of the sequential decoding algorithm

A systolic array processing technique is applied to implementing the stack algorithm form of the sequential decoding algorithm. It is shown that sorting, a key function in the stack algorithm, can be efficiently realized by a special type of systolic arrays known as systolic priority queues. Compared to the stack-bucket algorithm, this approach is shown to have the advantages that the decoding always moves along the optimal path, that it has a fast and constant decoding speed and that its simple and regular hardware architecture is suitable for VLSI implementation. Three types of systolic priority queues are discussed: random access scheme, shift register scheme and ripple register scheme. The property of the entries stored in the systolic priority queue is also investigated. The results are applicable to many other basic sorting type problems.

Chang, C. Y.↗
NASA NTRS1990

Digital carrier demodulator employing components working beyond normal limits

In a digital device, having an input comprised of a digital sample stream at a frequency F, a method is disclosed for employing a component designed to work at a frequency less than F. The method, in general, is comprised of the following steps: dividing the digital sample stream into odd and even digital samples streams each at a frequency of F/2; passing one of the digital sample streams through the component designed to work at a frequency less than F where the component responds only to the odd or even digital samples in one of the digital sample streams; delaying the other digital sample streams for the time it takes the digital sample stream to pass through the component; and adding the one digital sample stream after passing through the component with the other delayed digital sample streams. In the specific example, the component is a finite impulse response filter of the order ((N + 1)/2) and the delaying step comprised passing the other digital sample streams through a shift register for a time (in sampling periods) of ((N + 1)/2) + r, where r is a pipline delay through the finite impulse response filter.

Hurd, William J.↗
NASA NTRS1973

Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

Source record↗
NASA NTRS1992

A VLSI decomposition of the deBruijn graph

The nth order deBruijn graph Bn is the state diagram for an n-stage binary shift register. It is a directed graph with 2 to the n vertices, each labeled with an n-bit binary string, and 2 to the n+1 edges, each labeled with an (n+1)-bit binary string. It is shown that Bn can be built by appropriately connecting together with extra edges many isomorphic copies of a fixed graph, which is called a building block for Bn. The efficiency of such a building block is refined as the fraction of the edges of Bn which are present in the copies of the building block. It is then shown that for any alpha less than 1, there exists a graph which is a building block for Bn of efficiency greater than alpha for all sufficiently large n. The results are illustrated by showing how a special hierarchical family of building blocks has been used to construct a very large Viterbi decoder which will be used on the Galileo mission.

Collins, Oliver↗
NASA NTRS1992

AE 152 cascode readout for far-IR focal plane arrays

The Amber Engineering AE 152 readout is a 32-channel multiplexer built as part of the FIR focal plane array development effort for the Space Infrared Telescope Facility (SIRTF). The design of the device addresses a number of constraints peculiar to the operation of germanium photoconductors. In particular, the need for a very high level of bias stability is solved by a nonswitched operation of the first stage. Additionally, the readout was optimized for the detector capacitance expected of large bulk photoconductors (about 0.7 pF) and for the slow operating speeds anticipated for this astronomical application. Fabricated in a 1.25-micron C-MOS process, the circuit utilizes a cascode input stage to provide gain at the front end while avoiding the Miller effect. The AE 152 also includes an internal offset correction and a shift register multiplexer for the output. We present test data for this device at a variety of temperatures, and show read noises as low as 8 electrons at a temperature of 77 K.

Young, Erick T.↗
NASA NTRS1990

A bit serial sequential circuit

Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.

Hu, S.↗
NASA NTRS1994

Fast computational scheme of image compression for 32-bit microprocessors

This paper presents a new computational scheme of image compression based on the discrete cosine transform (DCT), underlying JPEG and MPEG International Standards. The algorithm for the 2-d DCT computation uses integer operations (register shifts and additions / subtractions only); its computational complexity is about 8 additions per image pixel. As a meaningful example of an on-board image compression application we consider the software implementation of the algorithm for the Mars Rover (Marsokhod, in Russian) imaging system being developed as a part of Mars-96 International Space Project. It's shown that fast software solution for 32-bit microprocessors may compete with the DCT-based image compression hardware.

Kasperovich, Leonid↗