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At least 145 records · Page 8

A verified design of a fault-tolerant clock synchronization circuit: Preliminary investigations

Schneider demonstrates that many fault tolerant clock synchronization algorithms can be represented as refinements of a single proven correct paradigm. Shankar provides mechanical proof that Schneider's schema achieves Byzantine fault tolerant clock synchronization provided that 11 constraints are satisfied. Some of the constraints are assumptions about physical properties of the system and cannot be established formally. Proofs are given that the fault tolerant midpoint convergence function satisfies three of the constraints. A hardware design is presented, implementing the fault tolerant midpoint function, which is shown to satisfy the remaining constraints. The synchronization circuit will recover completely from transient faults provided the maximum fault assumption is not violated. The initialization protocol for the circuit also provides a recovery mechanism from total system failure caused by correlated transient faults.

Miner, Paul S.↗

Noninertial coordinate time: A new concept affecting time standards, time transfers, and clock synchronization

Relativity compensations must be made in precise and accurate measurements whenever an observer is accelerated. Although many believe the Earth-centered frame is sufficiently inertial, accelerations of the Earth, as evidenced by the tides, prove that it is technically a noninertial system for even an Earth-based observer. Using the constant speed of light, a set of fixed remote clocks in an inertial frame can be synchronized to a fixed master clock transmitting its time in that frame. The time on the remote clock defines the coordinate time at that coordinate position. However, the synchronization procedure for an accelerated frame is affected, because the distance between the master and remote clocks is altered due to the acceleration of the remote clock toward or away from the master clock during the transmission interval. An exact metric that converts observations from noninertial frames to inertial frames was recently derived. Using this metric with other physical relationships, a new concept of noninertial coordinate time is defined. This noninertial coordinate time includes all relativity compensations. This new issue raises several timekeeping issues, such as proper time standards, time transfer process, and clock synchronization, all in a noninertial frame such as Earth.

Steven D. Deines↗

Optimistic barrier synchronization

Barrier synchronization is fundamental operation in parallel computation. In many contexts, at the point a processor enters a barrier it knows that it has already processed all the work required of it prior to synchronization. The alternative case, when a processor cannot enter a barrier with the assurance that it has already performed all the necessary pre-synchronization computation, is treated. The problem arises when the number of pre-sychronization messages to be received by a processor is unkown, for example, in a parallel discrete simulation or any other computation that is largely driven by an unpredictable exchange of messages. We describe an optimistic O(log sup 2 P) barrier algorithm for such problems, study its performance on a large-scale parallel system, and consider extensions to general associative reductions as well as associative parallel prefix computations.

Nicol, David M.↗

Frame synchronization at 300 Mbps and beyond

A prototype frame synchronizer card and its supporting VLSI components under development at the Goddard Space Flight Center that will operate at a minimum 300 Mbps while providing a full suite of programmable functions are presented. Cumulative quality data generation, onboard self diagnostics, and status/control processing are all integrated in this single card design. Consideration is given to the telemetry frame synchronizer subsystem and high-rate frame synchronizer specifications.

Wunderlich, Kristin↗

Fail-Safe Synchronizer For Power Supply

Fail-safe synchronizer feeds external synchronizing signal to switching power supply. When external synchronizing signal lost, it feeds signal from relaxation oscillator to power supply.

Katz, Richard B.↗

Using GLONASS signal for clock synchronization

Although in accuracy parameters GLONASS is correlated with GPS, using GLONASS signals for high-precision clock synchronization was, up to the recent time, of limited utility due to the lack of specialized time receivers. In order to improve this situation, in late 1992 the Russian Institute of Radionavigation and Time (RMT) began to develop a GLONASS time receiver using as a basis the airborne ASN-16 receiver. This paper presents results of estimating user clock synchronization accuracy via GLONASS signals using ASN-16 receiver in the direct synchronization and common-view modes.

Gouzhva, Yuri G.↗

GSOSTATS Database: USAF Synchronous Satellite Catalog Data Conversion Software. User's Guide and Software Maintenance Manual, Version 2.1

The United States Air Force (USAF) provides NASA Lewis Research Center with monthly reports containing the Synchronous Satellite Catalog and the associated Two Line Mean Element Sets. The USAF Synchronous Satellite Catalog supplies satellite orbital parameters collected by an automated monitoring system and provided to Lewis Research Center as text files on magnetic tape. Software was developed to facilitate automated formatting, data normalization, cross-referencing, and error correction of Synchronous Satellite Catalog files before loading into the NASA Geosynchronous Satellite Orbital Statistics Database System (GSOSTATS). This document contains the User's Guide and Software Maintenance Manual with information necessary for installation, initialization, start-up, operation, error recovery, and termination of the software application. It also contains implementation details, modification aids, and software source code adaptations for use in future revisions.

Mallasch, Paul G.↗

Enhanced mixing of multiple supersonic rectangular jets by synchronized screech

The objective of the present work is to study the mixing characteristics of a linear array of supersonic rectangular jets under conditions of screech synchronization. The screech synchronization at a fully expanded jet Mach number of 1.61 is achieved by a precise adjustment of the internozzle spacing. To our knowledge, such an experiment on the resonant mixing of screech synchronized multiple rectangular jets has not been reported before. The results are compared with the case where the screech was suppressed in the multijet configuration.

Taghavi, R.↗

A synchronous motor chopper for laboratory testing of detector systems in infrared astronomy

Airborne and ground-based IR telescopes have oscillating secondary mirrors to permit subtraction of background emission from the sky and telescope. These chopping mirrors are synchronized to a clock which may originate in the data acquisition system. For laboratory testing of detecting instruments with such data systems, externally synchronized chopped IR sources are required. We describe a laboratory chopper in which a synchronous motor is driven by 2-phase sinusoidal currents in sync with an external clock at frequencies from 5 to 50 Hz. This design is used with the KAO's facility sources, the Chopped Hotplate and the Portable Chopped Light Source (PCLS).

Baltz, James A.↗

Current Trend Towards Using Soft Computing Approaches to Phase Synchronization in Communication Systems

This paper surveys recent advances in communications that utilize soft computing approaches to phase synchronization. Soft computing, as opposed to hard computing, is a collection of complementary methodologies that act in producing the most desirable control, decision, or estimation strategies. Recently, the communications area has explored the use of the principal constituents of soft computing, namely, fuzzy logic, neural networks, and genetic algorithms, for modeling, control, and most recently for the estimation of phase in phase-coherent communications. If the receiver in a digital communications system is phase-coherent, as is often the case, phase synchronization is required. Synchronization thus requires estimation and/or control at the receiver of an unknown or random phase offset.

Drake, Jeffrey T.↗

Application of Soft Computing in Coherent Communications Phase Synchronization

The use of soft computing techniques in coherent communications phase synchronization provides an alternative to analytical or hard computing methods. This paper discusses a novel use of Adaptive Neuro-Fuzzy Inference Systems (ANFIS) for phase synchronization in coherent communications systems utilizing Multiple Phase Shift Keying (MPSK) modulation. A brief overview of the M-PSK digital communications bandpass modulation technique is presented and it's requisite need for phase synchronization is discussed. We briefly describe the hybrid platform developed by Jang that incorporates fuzzy/neural structures namely the, Adaptive Neuro-Fuzzy Interference Systems (ANFIS). We then discuss application of ANFIS to phase estimation for M-PSK. The modeling of both explicit, and implicit phase estimation schemes for M-PSK symbols with unknown structure are discussed. Performance results from simulation of the above scheme is presented.

Drake, Jeffrey T.↗

Robust Synchronization Schemes for Dynamic Channel Environments

Professor Xiong will investigate robust synchronization schemes for dynamic channel environment. A sliding window will be investigated for symbol timing synchronizer and an open loop carrier estimator for carrier synchronization. Matlab/Simulink will be used for modeling and simulations.

Xiong, Fugin↗

Production of minimally disturbed synchronous cultures of hematopoietic cells

A method is describedforproducing sizable quantities of synchronously dividing, minimally disturbed mammalian cells. Cultures were grown immobilized on surfaces such that cell division within the population resulted in the continuous release of synchronous newborn cells. As judged by the quality and duration of synchronous growth, cell size distributions, and DNA compositions, newborn mouse L1210 cells grew with a very high level of synchrony without overt evidence of growth disturbances. The technology should be applicable to a variety of hematopoietic cells, as evidenced by similar results with human MOLT-4 and U937 cell lines.

Non-NASA Center↗

A Self-Stabilizing Byzantine-Fault-Tolerant Clock Synchronization Protocol

This report presents a rapid Byzantine-fault-tolerant self-stabilizing clock synchronization protocol that is independent of application-specific requirements. It is focused on clock synchronization of a system in the presence of Byzantine faults after the cause of any transient faults has dissipated. A model of this protocol is mechanically verified using the Symbolic Model Verifier (SMV) [SMV] where the entire state space is examined and proven to self-stabilize in the presence of one arbitrary faulty node. Instances of the protocol are proven to tolerate bursts of transient failures and deterministically converge with a linear convergence time with respect to the synchronization period. This protocol does not rely on assumptions about the initial state of the system other than the presence of sufficient number of good nodes. All timing measures of variables are based on the node s local clock, and no central clock or externally generated pulse is used. The Byzantine faulty behavior modeled here is a node with arbitrarily malicious behavior that is allowed to influence other nodes at every clock tick. The only constraint is that the interactions are restricted to defined interfaces.

Malekpour, Mahyar R.↗

Digital Synchronizer without Metastability

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Simle, Robert M.↗

System and method for clock synchronization and position determination using entangled photon pairs

A system and method for clock synchronization and position determination using entangled photon pairs is provided. The present invention relies on the measurement of the second order correlation function of entangled states. Photons from an entangled photon source travel one-way to the clocks to be synchronized. By analyzing photon registration time histories generated at each clock location, the entangled states allow for high accuracy clock synchronization as well as high accuracy position determination.

Shih, Yanhua↗

Byzantine-fault tolerant self-stabilizing protocol for distributed clock synchronization systems

A rapid Byzantine self-stabilizing clock synchronization protocol that self-stabilizes from any state, tolerates bursts of transient failures, and deterministically converges within a linear convergence time with respect to the self-stabilization period. Upon self-stabilization, all good clocks proceed synchronously. The Byzantine self-stabilizing clock synchronization protocol does not rely on any assumptions about the initial state of the clocks. Furthermore, there is neither a central clock nor an externally generated pulse system. The protocol converges deterministically, is scalable, and self-stabilizes in a short amount of time. The convergence time is linear with respect to the self-stabilization period.

Malekpour, Mahyar R.↗

A Self-Stabilizing Distributed Clock Synchronization Protocol for Arbitrary Digraphs

This report presents a self-stabilizing distributed clock synchronization protocol in the absence of faults in the system. It is focused on the distributed clock synchronization of an arbitrary, non-partitioned digraph ranging from fully connected to 1-connected networks of nodes while allowing for differences in the network elements. This protocol does not rely on assumptions about the initial state of the system, other than the presence of at least one node, and no central clock or a centrally generated signal, pulse, or message is used. Nodes are anonymous, i.e., they do not have unique identities. There is no theoretical limit on the maximum number of participating nodes. The only constraint on the behavior of the node is that the interactions with other nodes are restricted to defined links and interfaces. We present an outline of a deductive proof of the correctness of the protocol. A model of the protocol was mechanically verified using the Symbolic Model Verifier (SMV) for a variety of topologies. Results of the mechanical proof of the correctness of the protocol are provided. The model checking results have verified the correctness of the protocol as they apply to the networks with unidirectional and bidirectional links. In addition, the results confirm the claims of determinism and linear convergence. As a result, we conjecture that the protocol solves the general case of this problem. We also present several variations of the protocol and discuss that this synchronization protocol is indeed an emergent system.

Malekpour, Mahyar R.↗