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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Fabrication of thin-film electronic devices with non-destructive wafer reuse

Thin-film electronic devices such as LED devices and field effect transistor devices are fabricated using a non-destructive epitaxial lift-off technique that allows indefinite reuse of a growth substrate. The method includes providing an epitaxial protective layer on the growth substrate and a sacrificial release layer between the protective layer and an active device layer. After the device layer is released from the growth substrate, the protective layer is selectively etched to provide a newly exposed surface suitable for epitaxial growth of another device layer. The entire thickness of the growth substrate is preserved, enabling continued reuse. Inorganic thin-film device layers can be transferred to a flexible secondary substrate, enabling formation of curved inorganic optoelectronic devices.

Forrest, Stephen R.↗
DOE OSTI2021

Fiber attach enabled wafer level fanout

A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

Ardalan, Shahab↗
DOE OSTI2023

Fiber attach enabled wafer level fanout

A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

Ardalan, Shahab↗
DOE OSTI2024

System and method for bending crystal wafers for use in high resolution analyzers

The invention provides a method for fabricating analyzers, the method comprising providing a radiation manipulating material on a first surface of a flexible support; contacting a second surface of the flexible support to a permeable mold, wherein the mold has a first flexible support contact surface and a second surface; and applying negative pressure to the second side of the flexible support to cause the flexible support to conform to the first flexible support contact surface of the mold. Also provided is a system for fabricating crystal analyzers, the system comprising crystal structures reversibly attached to a flexible support; a porous mold reversibly contacting the flexible support, wherein the mold defines a topography; and a negative pressure applied to the flexible support to cause the crystal structures to conform to the topography.

Said, Ayman H.↗
DOE OSTI2021

Erosion of focus rings in capacitively coupled plasma etching reactors

In plasma etching reactors, the structure surrounding the wafer, often called a focus ring (FR), plays an important role in maintaining uniform fluxes of reactants across the wafer. The FR is typically made of dielectric materials. During the plasma etching process, the sheath that forms over the wafer to accelerate ions anisotropically into the surface extends over the FR. Electrical charging of the FR modifies the sheath relative to that over the wafer. On the one hand, one wants the sheath to be uniform across the wafer-FR boundary to enable uniform fluxes to the edge of the wafer. On the other hand, maintaining a high voltage sheath over the FR will erode the FR, which is undesirable as the FR is a consumable component that must be periodically replaced in high volume manufacturing. In this work, we computationally investigated the consequences of dielectric constant ε of the FR materials on erosion of the FR. The series capacitance of the FR and its underlying structure is typically smaller than that of the wafer and its underlying structure. As a result, the FR charges quickly relative to the wafer, which then reduces the voltage across the sheath on top of the FR. The ion energy and angular distributions (IEADs) striking the FR are, therefore, generally lower in energy with a broader angular distribution. With ε = 2, the ion energies striking the middle to the outer edge of the FR are 30–180 eV, whereas for ε = 100, the ion energies are 120–380 eV. At the transition between the wafer and the FR, there is a skew in the IEAD as large as 15° that results from the difference in sheath thickness above the wafer and the FR. This skew and the erosion rate across the FR are functions of the dielectric constant of the FR material. With low ε, the FR charges quickly, less plasma is produced above the FR, and there is less voltage across the sheath that results in less FR erosion. Increasing ε of the FR produces a higher sheath voltage as well as higher ion fluxes over the FR, which increases erosion, while the skew at the edge of the wafer is less severe. Further, the material of the subsurface portion of the FR, which dominates its capacitance, is an important consideration in the design of the substrate assembly.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Amorphous 2D Materials – A Novel Platform for Remote Epitaxy and Nanopatterned Epitaxy of III-V Semiconductors with Low Decomposition Temperatures

III-V semiconductor materials such as indium phosphide (InP) offer outstanding photonic properties that outperforms silicon, but the cost of these wafers is extremely expensive. Although reusing original wafers can effectively minimize the cost, current techniques for wafer recycling of these substrates add significant costs in fabrication, nullifying the cost savings by reusing the wafers. Besides, unlike other III-V materials such as gallium arsenide (GaAs), commonly used epitaxial lift-off method for wafer recycling is not well studied for materials like InP due to lack of lattice-matched sacrificial layers, which makes reusing these wafers more difficult. Remote epitaxy and nanopatterned epitaxy are newly discovered methods that enable single-crystal growth of III-V semiconductor thin films and easy exfoliation of these grown films, thus promising for a new cost-effective pathway of reusing wafers. However, previous methods of transferring two-dimensional (2D) materials, which use polymethyl methacrylate (PMMA) or metal stressor layers to transfer 2D materials grown on foreign substrates like copper (Cu) or silicon carbide (SiC), introduce defects and damages on the 2D layer and/or substrates during the transfer process. Remote epitaxial and nanopatterned epitaxial films grown on the damaged 2D layer/substrate suffer from lower crystal quality and imperfect exfoliation, which undermines wafer reusability and device performance. Here we report the MBE growth of amorphous boron nitride (a-BN) on InP wafers at low temperature that enabled improved quality of remote epitaxial and nanopatterned epitaxial films and their perfect exfoliation. We show fully covered a-BN on InP substrates despite their low decomposition temperatures. The surface of a-BN coated InP substrate remains smooth with a RMS roughness of around 3Â. We also demonstrate 100% coverage of single-crystal InP thin films grown on a-BN, with the film's quality significantly improved compared to the case of transferred 2D materials. In addition, the growth and exfoliation were successfully repeated multiple times, proving the feasibility for InP wafer recycling. Through this low temperature MBE growth approach with remote epitaxy and nanopatterned epitaxy, we successfully demonstrate large-scale flexible thin film exfoliation and recycling of InP substrates, which will lead to new opportunities in InP thin film-based photonics and novel heterostructures with significantly reduced cost.

Lu, Kuangye↗
DOE OSTI2022

Amorphous 2D Materials – A Novel Platform for Remote Epitaxy and Nanopatterned Epitaxy of III-V Semiconductors with Low Decomposition Temperatures

III-V semiconductor materials such as indium phosphide (InP) offer outstanding photonic properties that outperforms silicon, but the cost of these wafers is extremely expensive. Although reusing original wafers can effectively minimize the cost, current techniques for wafer recycling of these substrates add significant costs in fabrication, nullifying the cost savings by reusing the wafers. Besides, unlike other III-V materials such as gallium arsenide (GaAs), commonly used epitaxial lift-off method for wafer recycling is not well studied for materials like InP due to lack of lattice-matched sacrificial layers, which makes reusing these wafers more difficult. Remote epitaxy and nanopatterned epitaxy are newly discovered methods that enable single-crystal growth of III-V semiconductor thin films and easy exfoliation of these grown films, thus promising for a new cost-effective pathway of reusing wafers. However, previous methods of transferring two-dimensional (2D) materials, which use polymethyl methacrylate (PMMA) or metal stressor layers to transfer 2D materials grown on foreign substrates like copper (Cu) or silicon carbide (SiC), introduce defects and damages on the 2D layer and/or substrates during the transfer process. Remote epitaxial and nanopatterned epitaxial films grown on the damaged 2D layer/substrate suffer from lower crystal quality and imperfect exfoliation, which undermines wafer reusability and device performance. Here we report the MBE growth of amorphous boron nitride (a-BN) on InP wafers at low temperature that enabled improved quality of remote epitaxial and nanopatterned epitaxial films and their perfect exfoliation. We show fully covered a-BN on InP substrates despite their low decomposition temperatures. The surface of a-BN coated InP substrate remains smooth with a RMS roughness of around 3Å. We also demonstrate 100% coverage of single-crystal InP thin films grown on a-BN, with the film's quality significantly improved compared to the case of transferred 2D materials. In addition, the growth and exfoliation were successfully repeated multiple times, proving the feasibility for InP wafer recycling. Through this low temperature MBE growth approach with remote epitaxy and nanopatterned epitaxy, we successfully demonstrate large-scale flexible thin film exfoliation and recycling of InP substrates, which will lead to new opportunities in InP thin film-based photonics and novel heterostructures with significantly reduced cost.

Lu, Kuangye↗
DOE OSTI2020

Systems and methods for crack detection

Embodiments related to systems and methods of crack detection in wafers (e.g., silicon wafers for photovoltaics, photovoltaic devices including silicon wafers) are disclosed. In some embodiments, an apparatus may include a light source configured to illuminate a side of a wafer and a camera directed towards a first face of the wafer. In some embodiments, a long axis of a field of view of the camera may be angled relative to a propagation direction of the light source. In some embodiments, at least a portion of the field of view of the camera is offset from the path of propagation of light emitted from the light source through the wafer. In some embodiments, at least a portion of a light beam may be oriented at a positive non-zero angle relative to the first face of the wafer, and a dimension of the light beam normal to the first face of the wafer may be larger than a thickness of the wafer.

14 SOLAR ENERGY↗
DOE OSTI2021

Method of fabricating photosensitive devices with reduced process-temperature budget

A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.

Kay, Randolph R.↗
DOE OSTI2020

Impact of undoped substrates on high performance silicon solar cells

Today's highest-efficiency silicon solar cells typically operate near the threshold between low-level and high-level injection. It is not well understood if pushing further into a regime in which the cell operating point is solidly in high-level injection at all times of the day has further benefits for the solar cell performance. From a reliability perspective, cells fabricated on lower doped silicon have a larger breakdown voltage. This advantage can affect the design of modules allowing higher voltages and a relaxation of the number of bypass diodes needed. In this project, we present a comprehensive assessment, both experimental and using simulation, of how bulk resistivity, light intensity, and operation temperature impact the performance of the silicon solar cell. This work incorporates a comprehensive device physics analysis assisted by numerical simulation. The source code is now available under General Public License (GPL3), and to further leverage the findings of this project and outreach people outside of the scientific community, we are working with www.pveducation.org (which receives >1 million visitors a year) to create interactive content using our simulation results. The simulation results indicate that high bulk resistivity wafers (>>10 Ωcm) require bulk Shockley-Read-Hall (SRH) lifetimes in the millisecond range to outperform wafers with standard bulk resistivities (<10 Ωcm). Additionally, above bulk resistivities of 10 Ωcm (the exact value depends on the bulk characteristics of the wafer), the cell efficiency is weakly dependent on the bulk resistivity. As a result, ingot manufactures may have an opportunity to further reduce wafer cost by growing higher resistivity ingots that are more tolerant to resistivity variations. This project is particularly relevant today, as solar cell architectures with improved surface passivation and milliseconds lifetimes wafers are commercially available, leveraging potential benefits of using higher bulk resistivities. Outside of interdigitated back contact (IBC) cell, reported studies on high resistivity silicon (>100 Ωcm) are very limited. To the best of our knowledge, this project provides for the first-time experimental insight on solar cells fabricated on wafers with bulk resistivities up to several thousand Ωcm, delivering a comprehensive vision of their performance under real-world temperature and light intensity operation conditions. We manufactured and characterized solar cells with bulk resistivities in the range of 1 Ωcm to >15k Ωcm. Under standard testing conditions (STC), we measured solar cells efficiencies over 20% over the entire range of bulk resistivities, using our baseline cell processing. To evaluate the cell performance in real-world operation conditions, the solar cells were measured at different temperatures (25-80°C) and at different light intensities (0.1-1 suns). The measurements show that the bulk resistivity does not impact the solar cell response to temperature and light intensity. Similar thermal coefficients (TC) were measured for standard and high bulk resistivities, and they are comparable with the TC values reported in the literature for standard bulk resistivities <10 Ωcm. After light soaking, the solar cell didn’t show signs of light-induced degradation (LID). This result was expected since n-type float zone (FZ) wafers were used in this work, i.e. low traces of boron and low concentration of oxygen (oxygen is typically found in the seed end of Czochralski (CZ) ingots). We measured for high bulk resistivities (>10 Ωcm) extremely high breakdown voltages (>1000V). In conclusion, the insight provided by this project can positively impact the levelized cost of energy (LCOE) of the photovoltaic systems through its effect on cell and ingot manufacturing yield, silicon cell power output, and module reliability.

14 SOLAR ENERGY↗
DOE OSTI2022

Fine Pitch Bonding for High Density Interconnects

CTE (coefficient of thermal expansion) mismatch between two wafers has potential for brittle failure when large areas are bonded on top of one another (wafer to wafer or wafer to die bonds). To address this type of failure, we proposed patterning a polymer around metallic interconnects. For this project, utilized benzo cyclobutene (BCB) to form the bond and accommodate stress. For the metal interconnects, we used indium. To determine the benefits of utilizing BCB, mechanical shear testing of die bonding with just BCB were compared to die bonded just with oxide. These tests demonstrated that BCB, when cured for only 30 minutes and bonded at 200°C, the BCB was able to withstand shear forces similar to oxide. Furthermore, when the BCB did fail, it experienced a more ductile failure, allowing the silicon to crack, rather than shatter. To demonstrate the feasibility of using BCB between indium interconnects, wafers were pattered with layers of BCB with vias for indium or ENEPIG (electroless nickel, electroless palladium, immersion gold). Subsequently, these wafers were pattered with a variety of indium or ENEPIG interconnect pitches, diameters, and heights. These dies were bonded under a variety of conditions, and those that held a bond, were cross-sectioned and imaged. Images revealed that certain bonding conditions allow for interconnects and BCB to achieve a void-less bond and thus demonstrate that utilizing polymers in place of oxide is a feasible way to reduce CTE stress.

36 MATERIALS SCIENCE↗