Performance characteristics and specification of PCM bit synchronizer/signal conditioners.
PCM bit synchronizer/signal conditioners performance characteristics and specification
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PCM bit synchronizer/signal conditioners performance characteristics and specification
Absolute value type of early-late gate bit synchronizer phase noise performance determined by Fokker-Planck method, comparing results with different circuits performance
Mathematical model for predicting performance degradation of MSFTP-2 bit synchronizer used in MSFN
Impact bit for cutting, collecting, and storing samples such as lunar rock cuttings
Bit error probability after decoding for binary perfect single error correcting codes
PCM/NRZ signal band-limiting effect on bit error probability, using sample detector
Two rotary diamond bit designs, one operating with a chip-flushing fluid, the second including auger section to remove drilled chips, enhance usefulness of tool for exploratory and industrial core-drilling of hard, abrasive mineral deposits and structural masonry.
Very long baseline interferometry /VLB1/ one-bit instrumentation using videotape recorders in geodetic and geophysical measurements
Absolute value type early-late gate bit synchronizer steady state phase noise performance evaluation by Fokker-Planck method
The results achieved toward developing a baseline communications channel model for studying low bit rate telemetry transmissions from Venus Planetary Explorer spacecraft are presented. The overall communications systems model, discrete channel model, input signal generation, and signal acquisition model are discussed. Discrete Fourier transform considerations, sampling routines, and flow charts are included.
Description of an on-line optimal (in the sense of linear minimum mean square error) sequential bit synchronizer assuming minimal a priori knowledge of the incoming data. The adaptive synchronization algorithms, implemented on a small computer, are capable of accurately estimating pulse transition time, pulse amplitude, and pulse width by invoking the powerful Gauss-Markov theorem. Numerous simulations indicate that the performance of the synchronizer is satisfactory from the point of view of the amount of data required and the speed of convergence.
This paper presents an adaptive estimation algorithm for bit synchronization, assuming that the parameters of the incoming data process are time-varying. Experiment results have proved that this synchronizer is workable either judged by the amount of data required or the speed of convergence.
A recursive procedure is derived for decoding of rate R=1/n binary convolutional codes which minimizes the probability of the individual decoding decisions for each information bit subject to the constraint that the decoding delay be limited to Delta branches. This new decoding algorithm is similar to, but somewhat more complex than, the Viterbi decoding algorithm. A real-time, i.e. fixed decoding delay, version of the Viterbi algorithm is also developed and used for comparison to the new algorithm on simulated channels. It is shown that the new algorithm offers advantages over Viterbi decoding in soft-decision applications such as in the inner coding system for concatenated coding.
A recursive procedure is derived for decoding of rate R = 1/n binary convolutional codes which minimizes the probability of the individual decoding decisions for each information bit, subject to the constraint that the decoding delay be limited to Delta branches. This new decoding algorithm is similar to, but somewhat more complex than, the Viterbi decoding algorithm. A real-time, i.e., fixed decoding delay, version of the Viterbi algorithm is also developed and used for comparison to the new algorithm on simulated channels. It is shown that the new algorithm offers advantages over Viterbi decoding in soft-decision applications, such as in the inner coding system for concatenated coding.
This report documents the analysis and experimental validation of the performance of various aspects of a high rate bit synchronizer.
This paper considers bit synchronization through the use of a separate clock signal which is either amplitude modulated onto or summed with the data signal. For continuous data transmission, such schemes are known to be inferior, in the sense of efficient use of power, to schemes which derive synchronization directly from the data signal. However, these techniques have application in burst systems such as spacecraft command systems, and in systems where receiver simplicity is more important than power conservation. For systems in which the composite data-clock signal subsequently modulates an RF carrier, it is shown that the summed clock signal performs slightly better than the AM clock signal, and that for both signal types, the optimum allocation of power between data and clock is approximately 9:1.
Two highly reliable codes termed "Modified b-adjacent interleaving codes" provide fail-safe operation of launch processing and control system in which common memory is coordination point for interconnection of up to 64 minicomputers. Codes detect and correct bit errors in computer data transmission.
Modular interface unit transfers data at high speeds along four channels. Device expedites variable-word-length communication between computers. Operation eases exchange of bit information by automatically reformatting coded input data and status information to match requirements of output.