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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

A 90 GHz Amplifier Assembled Using a Bump-Bonded InP-Based HEMT

We report on the performance of a novel W-band amplifier fabricated utilizing very compact bump bonds. We bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) onto a separately fabricated passive circuit having a GaAs substrate. The compact bumps and small chip size were used for efficient coupling and maximum circuit design flexibility. This new quasi-monolithic millimeter-wave integrated circuit (Q-MMIC) amplifier exhibits a peak gain of 5.8 dB at approx. 90 GHz and a 3 dB bandwidth of greater than 25%. To our knowledge, this is the highest frequency amplifier assembled using bump-bonded technology. Our bump-bonding technique is a useful alternative to the high cost of monolithic millimeter-wave integrated circuits (MMIC's). Effects of the bumps on the circuit appear to be minimal. We used the simple matching circuit for demonstrating the technology - future circuits would have all of the elements (resistors, via holes, bias lines, etc.) included 'in conventional MMIC's. Our design in different from other investigators' efforts in that the bumps are only 8 microns thick by 15 microns wide. The bump sizes were sufficiently small that the devices, originally designed for W-band hybrid circuits, could be bonded without alteration. Figure 3 shows the measured and simulated magnitude of S-parameters from 85-120 GHz, of the InP HEMT bump-bonded to the low noise amplifier (LNA) passive. The maximum gain is 5.8 dB at approx. 90 GHz, and gain extends to 117 GHz. Measurement of a single device (without matching networks) shows approx. 1 dB of gain at 90 GHz. The measured gain of the amplifier agrees well with the design in the center of the measurement band, and the agreement falls off at the band edges. Since no accommodation for the bump-bonding parasitics was made in the design, the result implies that the parasitic elements associated with the bonding itself do not dominate the performance of the LNA circuit. It should be noted that this amplifier was designed for good noise performance, which is why the input and output return losses are poorer than one would expect for an amplifier simply matched for gain. However, noise performance has not been measured at this time. While the agreement between modeled vs. experimental data is not exact, the data prove that bump-bonded technology can be used for amplifiers at frequencies at least as high as 100 GHz. JPL is pursuing this technology as a way to economically and quickly incorporate the best available HEMTs into a circuit with all of the reliability and circuit design flexibility offered by MMIC technology. We are currently using the technology to fabricate 4-stage, wide-band, W-band LNA's. We have also performed pull and shear tests which show that the bump bonds are sufficiently robust for any anticipated application.

Pinsukanjana, Paul R.↗
NASA NTRS1975

Design and development of a 5 kV isolated solid state switch

This paper describes the design and fabrication of a 5000 volt isolated hybrid switch developed by Hughes Aircraft Company under contract to NASA/Lewis. Hughes did the packaging design and NASA did the circuit design. This unique microcircuit is intended for use as a shorting switch for large extraterrestrial solar cell arrays. The packaging design for the 5 kV isolated hybrid switch is different from most hybrid microcircuits in that it utilizes a compartmentalized plastic case (a portion of which is encapsulated), is not hermetic, and is designed for high voltage operation.

Holbrook, R. J.↗
NASA NTRS1983

A 20-GHz IMPATT transmitter

The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band. The development effort involved a variety of disciplines including IMPATT device development, circulator design, simple and multiple diode circuits designs, and amplifier integration and test.

Chan, J. L.↗
NASA NTRS1993

Analog-To-Digital Converter For Sum-Of-Squares Measurements

Analog-to-digital converter (ADC) circuit designed as part of larger circuit intended to measure root-mean-square current on 20-kHz powerline. Provides digital output of 11 bits of data plus 1-bit overflow signal at sampling rate of 4 MHz. Output processed by multiplying-and-accumulating circuitry to obtain sum of squares and digitized current samples accumulated during preset number of consecutive sampling periods. Used to digitize current samples from ADC directly as alternative or auxiliary output. Notable features include low power and fast conversion.

Osborn, Stephen H.↗
NASA NTRS1992

Ultra-dense magnetoresistive mass memory

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Daughton, J. M.↗
NASA NTRS1997

Analysis of Smart Composite Structures Including Debonding

Smart composite structures with distributed sensors and actuators have the capability to actively respond to a changing environment while offering significant weight savings and additional passive controllability through ply tailoring. Piezoelectric sensing and actuation of composite laminates is the most promising concept due to the static and dynamic control capabilities. Essential to the implementation of these smart composites are the development of accurate and efficient modeling techniques and experimental validation. This research addresses each of these important topics. A refined higher order theory is developed to model composite structures with surface bonded or embedded piezoelectric transducers. These transducers are used as both sensors and actuators for closed loop control. The theory accurately captures the transverse shear deformation through the thickness of the smart composite laminate while satisfying stress free boundary conditions on the free surfaces. The theory is extended to include the effect of debonding at the actuator-laminate interface. The developed analytical model is implemented using the finite element method utilizing an induced strain approach for computational efficiency. This allows general laminate geometries and boundary conditions to be analyzed. The state space control equations are developed to allow flexibility in the design of the control system. Circuit concepts are also discussed. Static and dynamic results of smart composite structures, obtained using the higher order theory, are correlated with available analytical data. Comparisons, including debonded laminates, are also made with a general purpose finite element code and available experimental data. Overall, very good agreement is observed. Convergence of the finite element implementation of the higher order theory is shown with exact solutions. Additional results demonstrate the utility of the developed theory to study piezoelectric actuation of composite laminates with pre-existing debonding. Significant changes in the modes shapes and reductions in the control authority result due to partially debonded actuators. An experimental investigation addresses practical issues, such as circuit design and implementation, associated with piezoelectric sensing and actuation of composite laminates. Composite specimens with piezoelectric transducers were designed, constructed and tested to validate the higher order theory. These specimens were tested with various stacking sequences, debonding lengths and gains for both open and closed loop cases. Frequency changes of 15% and damping on the order of more than 20% of critical damping, via closed loop control, was achieved. Correlation with the higher order theory is very good. Debonding is shown to adversely affect the open and closed loop frequencies, damping ratios, settling time and control authority.

Chattopadhyay, Aditi↗
DOE OSTI2024

Approximate 𝑡-Designs in Generic Circuit Architectures

Unitary 𝑡-designs are distributions on the unitary group whose first 𝑡 moments appear maximally random. Previous work has established several upper bounds on the depths at which certain specific random quantum circuit ensembles approximate 𝑡-designs. Here we show that these bounds can be extended to any fixed architecture of Haar-random two-site gates. This is accomplished by relating the spectral gaps of such architectures to those of one-dimensional brickwork architectures. Our bound depends on the details of the architecture only via the typical number of layers needed for a block of the circuit to form a connected graph over the sites. When this quantity is bounded, the circuit forms an approximate 𝑡-design in at most linear depth. We give numerical evidence for a stronger bound that depends only on the number of connected blocks into which the architecture can be divided. We also give an implicit bound for nondeterministic architectures in terms of properties of the corresponding distribution over fixed architectures.

information scrambling↗
DOE OSTI2023

A Hardware and Software Co-design Framework for Energy Efficient Neuromorphic Systems

Neuromorphic systems can be realized by a variety of algorithms and architectures. A common understanding is that spiking neuromorphic designs, which encode information into spatio-temporal spiking events, are both a biologically-accurate and efficient way of processing information. However, representing the information through timing relationships induces sophisticated circuit designs in traditional CMOS-based implementations. In recent years, high-capacity resistive memory (RRAM, aka, memristor) has demonstrated great potential in mimicking synaptic behaviors. Several RRAM-based spiking neuromorphic designs exist, most of which focus on rate coding schemes. These designs simplify circuit implementations of neuron models and explore challenges such as unsatisfactory speed, resolution, and performance. As an alternative, we will explore temporal coding spiking neuromorphic systems that encode information as the relative timing of neuron activations (spikes), which have been proven to be more adaptive and energy-efficient. Developing a neuromorphic system for spiking neural network (SNN) inference and online training, however, faces some major technical challenges: (1) It lacks circuit implementation support for temporal-coding SNN to achieve satisfying power efficiency and accuracy; (2) Although existing research works have investigated memristive synapse and neuron designs for spike-timing-dependent plasticity, the non-ideal conditions in implementation, such as device variations and signal degradation, degrade online learning accuracy of large scale systems; and (3) Non-optimized, inter-layer data traffic in SNNs, leads to unnecessary data communication costs. In this project, we plan to address these challenges by a hardware and software co-design framework that incorporates solutions at the circuit, architecture, and algorithm levels. At the circuit-level, we will elaborate on the in-situ SNN processing element designs for supporting both inference and online training modes. Variation-aware schemes will be studied to improve reliability. At the architecture level, we propose a pipelined, asynchronous architecture to retain the timing resolution of spikes. At the algorithm level, we will investigate an innovative SNN training algorithm for enabling activation sparsification and reducing unnecessary data communication costs. This neuromorphic system will provide an effective solution to real-life energy-constrained applications and significantly contribute to the exploration of next-generation high-performance computing systems under the DOE context.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1973

Space shuttle main engine controller assembly, phase C-D

System design and system analysis and simulation are slightly behind schedule, while design verification testing has improved. Input/output circuit design has improved, but digital computer unit (DCU) and mechanical design continue to lag. Part procurement was impacted by delays in printed circuit board, assembly drawing releases. These are the result of problems in generating suitable printed circuit artwork for the very complex and high density multilayer boards.

Source record↗
NASA NTRS1980

Flat-plate photovoltaic array design optimization

An analysis is presented which integrates the results of specific studies in the areas of photovoltaic structural design optimization, optimization of array series/parallel circuit design, thermal design optimization, and optimization of environmental protection features. The analysis is based on minimizing the total photovoltaic system life-cycle energy cost including repair and replacement of failed cells and modules. This approach is shown to be a useful technique for array optimization, particularly when time-dependent parameters such as array degradation and maintenance are involved.

Ross, R. G., Jr.↗
NASA NTRS1991

An improved offset generator developed for Allan deviation measurement of ultra stable frequency standards

Measuring the performance of ultra stable frequency standards such as the Superconducting Cavity Maser Oscillator (SCMO) necessitates improvement of some test instrumentation. The frequency stability test equipment used at JPL includes a 1 Hz Offset Generator to generate a beat frequency between a pair of 100 MHz signals that are being compared. The noise floor of the measurement system using the current Offset Generator is adequate to characterize stability of hydrogen masers, but it is not adequate for the SCMO. A new Offset Generator with improved stability was designed and tested at JPL. With this Offset Generator and a new Zero Crossing Detector, recently developed at JPL, the measurement flow was reduced by a factor of 5.5 at 1 second tau, 3.0 at 1000 seconds, and 9.4 at 10,000 seconds, compared against the previous design. In addition to the new circuit designs of the Offset Generator and Zero Crossing Detector, tighter control of the measurement equipment environment was required to achieve this improvement. The design of this new Offset Generator are described, along with details of the environment control methods used.

R. L. Hamell↗
NASA NTRS1988

Designing A Microwave Band-Stop Filter

Lumped-circuit design techniques applied to iris-coupled cavities. Waveguide/cavity filter imitates lumped series and parallel combinations of inductance and capacitance over narrow stopband centered at 7.190 GHz. Filter made of standard WR125 waveguide stock.

Manshadi, F.↗
NASA NTRS2006

Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

integrated circuit testing↗
DOE OSTI2026

Booster cavity damper redesign for PIP-II

A new Higher Order Mode (HOM) damper was designed and is undergoing testing for the Booster accelerator cavity at Fermilab. In anticipation of the PIP-II upgrade, it was discovered that the higher intensity of PIP-II may cause beam instability due to an excited mode at 106 MHz. This unfortunately corresponds with the cavity’s 2nd order harmonic mode, which will sweep from 86-105.7 MHz. The new damper is a modification of an existing damper that was designed to reduce an existing static HOM at 83 MHz, with the new design intending to cover the 2nd order HOM as well. The existing damper uses an inductive coupling loop to extract RF energy from the cavity which then goes through a filter in order to reflect the fundamental frequency back into the cavity while passing HOMs to a dump load. The new damper intends to replace the filter portion of the system with a wider band variant while also changing the topology from a coaxial cable loop filter to a componentized PCB-based design. Primary design challenges include bandwidth coverage, impedance matching of the various modes, long term thermal and mechanical stability, radiation hardness, and high voltage handling. Initial designs achieved the desired damping but were found to quickly succumb to destructive arcing due to the voltages present. More finalized designs intend to address this problem through circuit design modifications as well as the use of hardier components.

Pieper, Dustin [Fermilab]↗
DOE OSTI2025

Booster Cavity Damper Redesign for PIP-II

A new Higher Order Mode (HOM) damper was designed and tested for the Booster accelerator cavity at Fermilab. In anticipation of the PIP-II upgrade, it was discovered that the higher beam intensity of PIP-II may cause beam instability due to an excited mode at 106 MHz. This unfortunately corresponds with the cavity s 2nd order harmonic mode, which will sweep from 86-105.7 MHz. The new damper is a modification of an existing damper that was designed to reduce an existing static HOM at 83 MHz, with the new design intending to cover the 2nd order HOM as well. The existing damper uses an inductive coupling loop to extract RF energy from the cavity which then goes through a filter in order to reflect the fundamental frequency back into the cavity while passing HOMs to a dump load. The new damper intends to replace the filter portion of the system with a wider band variant while also changing the topology from a coaxial cable loop filter to a componentized PCB-based design. Primary design challenges include bandwidth coverage, impedance matching of the various modes, long term thermal and mechanical stability, radiation hardness, and high voltage handling. Initial designs achieved the desired damping but were found to quickly succumb to destructive arcing due to the voltages present. More finalized designs intend to address this problem through circuit design modifications as well as the use of hardier components.

Pieper, Dustin [Fermilab]↗