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At least 145 records · Page 8

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DOE OSTI2024

PHIL Interface Design for Use With a Voltage-Regulated Amplifier

Power hardware-in-the-loop (PHIL) has emerged as a leading strategy to thoroughly assess the impact of proprietary inverter controls on a specific power system. The development of a PHIL test bed typically involves an inverter under test, a power amplifier, controllable DC supply, and a digital real-time simulator (DRTS) to simulate the power system under study. As a result of PHIL nonidealities, a form of digital compensation within the DRTS is used, which is commonly referred to as a PHIL interface. Many existing methods use legacy power amplifiers that do not contain internal voltage regulation. These existing interface methods are based around a voltage regulator within the DRTS and do not consider the interaction with the controls in newer amplifiers. In this study, a three-step approach of PHIL interface development for modern power amplifiers with built-in voltage regulation is introduced and is validated in hardware with a 30-kW grid-following inverter.

DRTS↗

DOE OSTI2026

qSIEVE: Efficient qLDPC Memory via Systolic Movement in Atom Arrays

As quantum machines have scaled up in their number of qubits, significant research has turned towards increasing their fidelity with quantum error correction codes. Although promising results have been shown with the surface code, which only requires near-neighbor connections between qubits, the high qubit overhead of such local codes promises to be problematic. Consequently, recent work has explored non-local quantum LDPC (qLDPC) codes, which have good asymptotic encoding rates. Despite theoretical progress, hardware implementations of these codes have been a longstanding challenge. At the experimental level, demonstrations of movement based communication on atom arrays suggest this is a powerful new primitive to achieve non-local connectivity. Leveraging this, we present a protocol for implementing non-local qLDPC codes in hardware. Our protocol, qSIEVE, is a co-design of such codes with movement in atom arrays. qSIEVE defines a restricted family of qLDPC codes that can be implemented efficiently with systolic movement. We then quantify the utility of qSIEVE in the context of a complete fault tolerant architecture. We compare the cost of implementing benchmark programs in a standard, surface code only architecture and a mixed architecture where data is stored in qLDPC memory with qSIEVE and loaded to surface codes for computation.

Quantum error correction↗

DOE OSTI2025

Quantum Information for Fusion Energy Sciences (Final Technical Report)

The simulation of plasma dynamics is a critical area of Fusion Energy Sciences (FES) due to it’s usefulness in predicting, controlling, and confining plasmas in the context of potential fusion reactors. The simulation of plasmas is a computationally difficult problem in both classical and quantum physics, motivating investigation into the potential of quantum computers to simulate these systems. This project took several concrete steps towards this goal by developing tools for improving the control, characterization, and calibration of quantum gates on a superconducting quantum computer, developing error suppression and mitigation tools to reduce errors on the quantum computer, and utilizing these advancements to simulate reduced models of plasma dynamics on the quantum computer. In order to efficiently simulate plasma physics, an optimal control method which synthesizes, directly at the pulse level, any quantum gate on qubit and qutrit systems was developed. Using four superconducting transmon quantum processors at Rigetti and LLNL, it was demonstrated that any arbitrary quantum gate on qubits and qutrits could be implemented with high fidelity, leading to a significantly reduced length of a gate sequence. A problem of interest in FES is the nonlinear optical process of laser pulse compression within a plasma. Since quantum physics is linear, simulating nonlinear operations is not naturally feasible on a quantum computer, however it is possible to simulated a quantized version of the nonlinear process. A quantization approach to convert nonlinear wave-wave interaction problems to Hamiltonian simulation problems was developed and demonstrated using two qubits on a Rigetti device. In this experiment, a number of error suppression and mitigation techniques were investigated to determine how best to utilize the finite quantum resources. This study provides an example of how plasma problems may be solved on near-term, noisy quantum computing platforms and identified a promising set of techniques. Building on the insights of these experiments, the investigation turned to linear electron-plasma wave physics. A connection was identified between a local one-dimensional lattice spin model and linear wave phenomena, allowing a plasma physics problem to be efficiently mapped to the quantum computer. In this framework, reflection and transmission of plasma waves at a sharp boundary was studied, as well as the propagation of waves through an inhomogeneous plasma medium. In addition to the suite of error suppression and mitigation techniques developed, this experiment introduced the use of a digital-analog gate scheme designed to efficiently simulate the plasma Hamiltonian. With hardware available at the conclusion of the project, simulation at the scale of 9 qubits and 15 timesteps (60 entangling layers) was achieved.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

DOE OSTI2026

Solar Photovoltaics Resilient Fasteners Levelized Cost of Energy (LCOE) Tool

Solar photovoltaics (PV) module fasteners are one of the most common structural failure points on PV systems, particularly in high winds and coastal areas with ocean spray. Some fastener types have been shown to survive these conditions at higher rates than others. The fastener type, material, quantity, and placement all impact performance. Fasteners that fail less often typically have a higher upfront cost, but this investment can pay off in savings from less frequent torque audits (which reduces O&M costs), reduced system damage, and decreased system downtime. We developed an Excel-based tool to evaluate different module fasteners for a PV system - either a new or retrofit project - and compare differences in upfront and outyear costs to determine the expected life cycle costs and simple payback periods of different fastener options. The tool is site-specific, with inputs including system attributes (such as system size, location, price of power) and fastener attributes (such as design, washer type, nut type, use of locking hardware, materials, installation time, and torque audit requirements). A baseline fastener scenario can be compared to up to four proposed fastener scenarios. In addition to presenting expected life cycle cost implications of the different fastener options, the tool produces results showing the reductions in outyear costs needed to offset any initial cost premiums for more reliable fasteners across four categories: preventative O&M, avoided damage, reduced downtime, and reduced insurance premiums. These numbers can serve as decision aids for users when considering fastener options on new or existing projects. This poster will present the tool, methodology, and scenarios using example sites to highlight the tool capabilities and how it can inform different fastener decisions on different projects. Future work includes incorporating lifetime expected damage costs by embedding damage function curves that the authors are developing from field data.

14 SOLAR ENERGY↗

DOE OSTI2026

ORCHA: A performance portability system for extreme heterogeneity

Heterogeneity is the prevalent trend in the rapidly evolving high-performance computing (HPC) landscape in both hardware and application software. The diversity in hardware platforms, currently comprising various accelerators and a future possibility of specializable chiplets, poses a significant challenge for scientific software developers aiming to harness optimal performance across different computing platforms while maintaining the quality of solutions when their applications are simultaneously growing more complex. Code synthesis and code generation can provide mechanisms to mitigate this challenge. We have developed a divide and conquer approach where different aspects of performance are handled by different stand-alone tools that are interfaced with the application through generated code. This portability system, ORCHA, enables users to configure and orchestrate their computations among available resources on a platform by specifying a high-level recipe, thereby permitting a many-to-many paradigm where each recipe results in a different variant of the application. The core design goal is to let users decide the application’s hardware mapping and orchestration by editing only the high-level recipe—without modifying the maintained source code or binding the application to a particular runtime system. Tools in ORCHA distribution are: CG-Kit for translating the recipe into an execution graph; Milhoja to execute the graph by orchestrating data and task movement among hardware resources; and Macroprocessor that enables users to define their own code-shorthand for higher composability and easier management of code variants. Additionally, the design of ORCHA permits tools to work in a plug-and-play mode where the application can build and run without CG-Kit and Milhoja, and either tool can be swapped out for other tools with similar capabilities by modifying the code generation portion of ORCHA. In this paper, we describe the design of ORCHA and the role that code-generation plays in isolating applications from tools. We demonstrate the breadth of configurations ORCHA enables with a case study in which an application configuration is realized on three distinct hardware mappings—a GPU-centric, a CPU/GPU balanced, and a CPU/GPU concurrent layouts by using different recipes.

Lee, Youngjun↗

DOE OSTI2024

Advances on CHP District Energy and Microgrids Deployment: Simplified Tool for Rapidly Deploying Feasibility Analytics for the Non-Technical User (Final Technical Report)

Community energy systems have proven to have the potential to improve cost efficiency, resilience, and decarbonize. However, investing in community energy systems such as community microgrids or district energy systems is a complex decision due to the high initial investment and the uncertainties associated with the long development time and lifecycle of the project. Tools that make feasibility assessments accessible to non-technical users like investors, policymakers, and other stakeholders will result in more feasibility analyses completed, more candidate projects identified, and more community energy systems deployed. The pilot tool developed under this award is named Energy Fellow. Energy Fellow allows technical and non-technical users to complete feasibility analyses for district energy systems and community microgrids. This is the first software tool of its kind designed for non-technical users and available at no cost. Its scope was adjusted to a 25x25-mile region within the Houston area in Texas to make its development compatible with the funding available. However, the findings and models developed make this pilot tool easily scalable to the US. The lessons learned during the design, implementation, and testing stages have helped find trade-off solutions to software and hardware challenges related to implementing 3D models in online tools. Green software strategies has been successfully applied to the design and operations of the tool, and the team has researched the aspects of the (non-technical) user experience that will make commercial developments of this tool even more impactful.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗

DOE OSTI2026

Quantum Computing and Visualization Research Challenges and Opportunities

Here, quantum computing (QC) has experienced rapid growth in recent years with the advent of robust programming environments, readily accessible software simulators and cloud-based QC hardware platforms, and growing interest in learning how to design useful methods that leverage this emerging technology for practical applications. From the perspective of the field of visualization, this article examines research challenges and opportunities along the path from initial feasibility to practical use of QC platforms applied to meaningful problems.

Data visualization↗

DOE OSTI2026

Multi-Split Variable Refrigerant Flow (VRF) System Building Energy Simulations Using Performance Maps

Multi-split variable refrigerant flow (VRF) systems are highly energy-efficient HVAC (heating, ventilation and air conditioning) technologies that connect a single outdoor unit to multiple independent indoor terminal units using a common refrigerant circuit and a variable-speed compressor. Building energy simulations that incorporate VRF systems help model their unique operational characteristics and predict energy consumption in specific building designs. Traditionally, EnergyPlus models these systems by employing multiple sets of performance curves to characterize both individual terminal units and the outdoor unit. However, producing these curves is labor intensive and error prone, and they often do not capture all the key input and output variables. This paper introduces a novel approach that uses multi-dimensional performance maps to model VRF systems in building environments for space cooling. In this approach, performance maps are developed at the component level—separately for the outdoor unit and for each indoor terminal. The new modeling method is validated within EnergyPlus via a Python plug-in that contains a simple solver loop to coordinate the component-level, indoor, and outdoor unit maps. Furthermore, because performance maps can span more variables than traditional performance curves, they offer the opportunity to implement advanced controls, such as enhanced dehumidification and compressor modulation. A VRF air conditioner’s hardware system was modeled using the DOE/ORNL Heat Pump Design Model, which was automated to produce extensive performance maps for both the indoor and outdoor units.

Shen, Bo [ORNL] (ORCID:0000000336600393)↗

DOE OSTI2025

Design, Control, and Protection of a 13.2 kV, 1 MVA Solid State Transformer for Electric Vehicle Extreme Fast Charging Station

In this article, a medium-voltage (MV) ac-dc solid state transformer (SST) for electric vehicle (EV) extreme fast charging (XFC) station is proposed. The SST adopts a cascaded H-bridge (CHB)-based structure where the active front end (AFE) power stages are connected in input-series followed by dual active bridge (DAB) converters connected in an output-parallel configuration providing galvanic isolation through a high-frequency transformer (HFT). The SST is rated for 1 MVA and connects directly to a three-phase 13.2 kV MV ac grid through ac switchgear and outputs 750-V dc. At the dc bus, several dc/dc converters are connected, each of which can charge an EV based on its battery capacity. A novel decentralized control architecture of the SST is adopted in this work which simplifies the MV dc link voltage and module-level power balancing. In addition, the local and central protection designs of the SST are presented which identify and respond to the internal fault of the system. Finally, the experimental validations of the SST hardware prototype are presented up to the rated voltage. Furthermore, this article details the design and implementation of the MV SST addressing the challenges of an isolated MV class power converter for connecting directly to the MV ac grid with unique controller architecture, distributed protection framework, and SST constructional features.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

DOE OSTI2025

Advantages of imperfect dice rolls over coin flips for random number generation

With an eye toward neural-inspired probabilistic computation, recent work has examined the development of true random number generators via stochastic devices. Typically, these devices are operated in a two-state regime to produce a sequence of binary outcomes (i.e., coin flips). However, there is no guarantee that stochastic devices will infallibly produce fair outputs and small deviations from a uniform distribution may have unwanted complications in applications. Using mathematical analysis, we contend that opting instead for a multi-state device (i.e., a dice roll) has benefits in these unfair paradigms. To demonstrate these benefits, we apply this framework to the analysis of a tunnel diode operated in a stochastic regime. In particular, interpreting the binary stochastic output of the tunnel diode as a multi-state die roll output also sees advantages in remaining closer to uniform. Overall, our approach provides a compelling argument for mathematical driven co-design and development of novel probabilistic computing devices and hardware.

applied mathematics↗

DOE OSTI2026

A Unified Wireless Charger, On-Board Charger, and Auxiliary Power Module for Electric Vehicle Charging Systems

This paper proposes a unified electric vehicle (EV) charging architecture that integrates wireless power transfer (WPT), an on-board charger (OBC), and an auxiliary power module (APM) within a single architecture. By sharing a multi-functional magnetic structure and active switch bridges, the proposed topology eliminates additional transformers and converter stages, reducing hardware complexity and improving power density. A multipurpose magnetic design achieves magnetic decoupling among the WPT, OBC, and APM functions while maintaining the required coupling for each mode. Through electrical reconfiguration, the WPT operates as an LCC-S converter, whereas the OBC and APM operate as dual-active-bridge (DAB) converters. The system supports multiple operating modes, including simultaneous high-voltage and lowvoltage battery charging. Finite-element and circuit simulations verify the magnetic characteristics and system operation, demonstrating the feasibility of the proposed unified architecture for EV charging applications.

Jo, Cheolhui [ORNL] (ORCID:0000000322692434)↗

DOE OSTI2025

AutoFocus: AI/ML-driven real-time wavefront diagnostics to autonomously align and optimize X-ray optics

We present an integrated system that combines advanced wavefront diagnostics with artificial intelligence (AI) to automate and optimize X-ray optics at synchrotron beamlines. This system couples real-time wavefront sensing with AI-driven control algorithms to achieve precise beam alignment, stabilization, and performance optimization. A key feature is the use of multi-fidelity transfer learning, which enables knowledge gained from both real-world beamline optimizations and ultra-realistic digital twin simulations to be effectively applied to in situ optimization. By leveraging multi-objective bayesian optimization, the system continuously refines its performance, reducing optimization time and minimizing the need for manual adjustments. Designed for seamless deployment, it operates with existing beamline hardware and provides an intuitive graphical interface. Initial deployments at the advanced photon source beamlines have demonstrated its ability to enhance beam stability, improve reproducibility, and significantly streamline alignment procedures. This AI-enhanced control framework represents a significant step toward fully autonomous beamline operation in next-generation synchrotron facilities.

Rebuffi, Luca [Argonne National Laboratory (ANL), ↗

DOE OSTI2026

wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation

As machine learning (ML) is increasingly implemented in hardware to address real-time challenges in scientific applications, the development of advanced toolchains has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as hardware synthesis, are becoming limiting factors in the rapid iteration of designs. To mitigate these emerging constraints, multiple efforts have been undertaken to develop an ML-based surrogate model that estimates resource usage of ML accelerator architectures. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of over 680,000 fully connected and convolutional neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, and the average performance across a subset of the dataset. Additionally, we introduce GNN- and transformer-based surrogate models that predict latency and resources for ML accelerators. We present the architecture and performance of the models and find that the models generally predict latency and resources for the 75% percentile within several percent of the synthesized resources on the synthetic test dataset.

Hawks, Benjamin [Fermilab] (ORCID:0000000157000288↗

DOE OSTI2025

wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation

As machine learning (ML) is increasingly implemented in hardware to address real-time challenges in scientific applications, the development of advanced toolchains has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as hardware synthesis, are becoming limiting factors in the rapid iteration of designs. To mitigate these emerging constraints, multipleefforts have been undertaken to develop an ML-based surrogate model that estimates resource usage of synthesized ML accelerator architectures. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of over 680 000 fully connected and convolutional neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, and the average performance across a subset of the dataset. Additionally, we introduce GNN- and transformer-based surrogate models that predict latency and resources for ML accelerators. We present the architecture and performance of the models and find that the models generally predict latency and resources for the 75% percentile within several percent of the synthesized resources on the synthetic test dataset.

Hawks, Benjamin G. [Fermilab]↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2024

Hardware-in-the-loop Laboratory Performance Verification of Flexible Building Equipment in a Typical Commercial Building

This project aims to develop high-resolution equipment performance and occupant data that quantifies demand flexibility in typical commercial buildings. The dataset documented in this report includes comprehensive time-series measurements from hardware-in-the-loop (HIL) experiments conducted across multiple testbeds designed to simulate realistic operational environments for HVAC systems. Specifically, it captures minute-by-minute high-resolution data on the performance of various typical HVAC systems, including a variable-air-volume (VAV) air handling unit (AHU) system with chillers and an ice tank in the Intelligent Building Agents Laboratory (IBAL) at the National Institute of Standards and Technology (NIST), a two-stage air-source heat pump (ASHP) at the NIST, and a water-source heat pump (WSHP) at Texas A&M University (TAMU). The data were generated under a range of controlled conditions reflecting different grid scenarios and climatic influences, as well as various control strategies, building types, occupancy patterns, and occupant behaviors. This dataset provides DE-EE0009153 Final Report 5 detailed insights into the demand flexibility of these systems, including their response to grid signals, occupant behaviors, energy consumption patterns, and operational efficiency under different conditions.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

DOE OSTI2025

QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures

Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.

Yin, Keyi [University of California, San Diego]↗